MIMXRT1050-EVK
Overview
The i.MX RT1050 is a new processor family featuring NXP’s advanced implementation of the ARM Cortex-M7 Core. It provides high CPU performance and real-time response.
The i.MX RT1050 provides various memory interfaces, including SDRAM, Raw NAND FLASH, NOR FLASH, SD/eMMC, Quad SPI, HyperBus and a wide range of other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, displays, and camera sensors. As with other i.MX processors, i.MX RT1050 also has rich audio and video features, including LCD display, basic 2D graphics, camera interface, SPDIF, and I2S audio interface.
Hardware
MIMXRT1052DVL6A MCU (600 MHz, 512 KB TCM)
Memory
256 KB SDRAM
64 Mbit QSPI Flash
512 Mbit Hyper Flash
Display
LCD connector
Touch connector
Ethernet
10/100 Mbit/s Ethernet PHY
USB
USB 2.0 OTG connector
USB 2.0 host connector
Audio
3.5 mm audio stereo headphone jack
Board-mounted microphone
Left and right speaker out connectors
Power
5 V DC jack
Debug
JTAG 20-pin connector
OpenSDA with DAPLink
Sensor
FXOS8700CQ 6-axis e-compass
CMOS camera sensor interface
Expansion port
Arduino interface
CAN bus connector
For more information about the MIMXRT1050 SoC and MIMXRT1050-EVK board, see these references:
External Memory
This platform has the following external memories:
Device |
Controller |
Status |
|---|---|---|
IS42S16160J |
SEMC |
Enabled via device configuration data block, which sets up SEMC at boot time |
S26KS512SDPBHI020 |
FLEXSPI |
Enabled via flash configuration block, which sets up FLEXSPI at boot time. |
Supported Features
The mimxrt1050_evk board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M7 CPU1 |
|
ADC |
on-chip |
||
ARM architecture |
on-chip |
MCUX XBAR (Crossbar)3 |
|
CAN |
on-chip |
NXP FlexCAN controller2 |
|
on-chip |
NXP FlexCAN CANFD controller1 |
||
Clock control |
on-chip |
i.MX CCM (Clock Controller Module) IP node1 |
|
on-chip |
Generic fixed factor clock provider3 |
||
on-chip |
i.MX CCM Fractional PLL1 |
||
on-chip |
i.MX ANATOP (Analog Clock Controller Module) IP node1 |
||
on-chip |
Generic fixed-rate clock provider4 |
||
Counter |
on-chip |
NXP MCUX Quad Timer (QTMR)4 |
|
on-chip |
NXP MCUX Quad Timer Channel16 |
||
on-chip |
NXP Periodic Interrupt Timer (PIT)1 |
||
on-chip |
Child node for the Periodic Interrupt Timer node, intended for an individual timer channel4 |
||
Cryptographic accelerator |
on-chip |
NXP Data Co-Processor (DCP) Crypto accelerator1 |
|
Debug |
on-chip |
ARMv7 instrumentation trace macrocell1 |
|
Display |
on-chip |
NXP i.MX eLCDIF (Enhanced LCD Interface) controller1 |
|
DMA |
on-chip |
NXP MCUX EDMA controller1 |
|
on-chip |
NXP PXP 2D DMA engine1 |
||
Ethernet |
on-chip |
NXP ENET IP Module1 |
|
on-chip |
NXP ENET MAC/L2 Device1 |
||
on-board |
Microchip KSZ8081 Ethernet PHY device1 |
||
on-chip |
NXP ENET PTP (Precision Time Protocol) Clock1 |
||
GPIO & Headers |
on-chip |
i.MX GPIO5 |
|
on-board |
GPIO pins exposed on NXP LCD interface1 |
||
on-board |
GPIO pins exposed on NXP LCD touch controller interface1 |
||
on-board |
GPIO pins exposed on Arduino Uno (R3) headers1 |
||
I2C |
on-chip |
||
I2S |
on-chip |
NXP mcux SAI-I2S controller3 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv7-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MDIO |
on-chip |
NXP ENET MDIO Features1 |
|
Memory controller |
on-chip |
NXP FlexRAM on-chip ram controller If the flexram,bank-spec property is specified, then the flexram will be dynamically reconfigured to the configuration specified at runtime1 |
|
on-chip |
NXP Smart External Memory Controller (SEMC)1 |
||
Miscellaneous |
on-chip |
NXP FlexIO controller2 |
|
MMU / MPU |
on-chip |
ARMv7-M Memory Protection Unit (MPU)1 |
|
MTD |
on-board |
NXP FlexSPI HyperFlash1 |
|
on-board |
Fixed partitions of a flash (or other non-volatile storage) memory1 |
||
Pin control |
on-chip |
This compatible binding should be applied to the device’s iomuxc DTS node1 |
|
on-chip |
The node has the ‘pinctrl’ node label set in MCUX RT SoC’s devicetree1 |
||
on-chip |
i.MX IOMUXC1 |
||
PWM |
on-chip |
NXP eFLEX PWM module with mcux-pwm submodules4 |
|
on-chip |
NXP MCUX PWM16 |
||
RNG |
on-chip |
Kinetis TRNG (True Random Number Generator)1 |
|
RTC |
on-chip |
NXP SNVS LP/HP RTC1 |
|
SDHC |
on-chip |
||
Sensors |
on-board |
FXOS8700 6-axis accelerometer/magnetometer sensor1 |
|
on-chip |
NXP MCUX QDEC4 |
||
on-chip |
NXP on-die temperature monitor1 |
||
Serial controller |
on-chip |
||
SPI |
on-chip |
||
on-chip |
|||
Timer |
on-chip |
ARMv7-M System Tick1 |
|
on-chip |
NXP MCUX General-Purpose HW Timer (GPT)1 |
||
on-chip |
NXP MCUX General-Purpose Timer (GPT)1 |
||
USB |
on-chip |
||
on-chip |
NXP USB high speed phy that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis platforms if high speed usb is supported on these platforms2 |
||
Video |
on-chip |
NXP MCUX CMOS sensor interface1 |
|
Watchdog |
on-chip |
Note
For additional features not yet supported, please also refer to the MIMXRT1064-EVK , which is the superset board in NXP’s i.MX RT10xx family. NXP prioritizes enabling the superset board with NXP’s Full Platform Support for Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1050_evk board.
Connections and IOs
The MIMXRT1050 SoC has five pairs of pinmux/gpio controllers.
Name |
Function |
Usage |
|---|---|---|
GPIO_AD_B0_00 |
LPSPI1_SCK |
SPI |
GPIO_AD_B0_01 |
LPSPI1_SDO |
SPI |
GPIO_AD_B0_02 |
LPSPI3_SDI/LCD_RST| SPI/LCD Display |
|
GPIO_AD_B0_03 |
LPSPI3_PCS0 |
SPI |
GPIO_AD_B0_05 |
GPIO |
SD Card |
GPIO_AD_B0_09 |
GPIO/ENET_RST |
LED |
GPIO_AD_B0_10 |
GPIO/ENET_INT |
GPIO/Ethernet |
GPIO_AD_B0_11 |
GPIO |
Touch Interrupt |
GPIO_AD_B0_12 |
LPUART1_TX |
UART Console |
GPIO_AD_B0_13 |
LPUART1_RX |
UART Console |
GPIO_AD_B1_00 |
LPI2C1_SCL |
I2C |
GPIO_AD_B1_01 |
LPI2C1_SDA |
I2C |
GPIO_AD_B1_06 |
LPUART3_TX |
UART BT HCI |
GPIO_AD_B1_07 |
LPUART3_RX |
UART BT HCI |
GPIO_AD_B1_11 |
ADC |
ADC1 channel 0 |
WAKEUP |
GPIO |
SW0 |
GPIO_B0_00 |
LCD_CLK |
LCD Display |
GPIO_B0_01 |
LCD_ENABLE |
LCD Display |
GPIO_B0_02 |
LCD_HSYNC |
LCD Display |
GPIO_B0_03 |
LCD_VSYNC |
LCD Display |
GPIO_B0_04 |
LCD_DATA00 |
LCD Display |
GPIO_B0_05 |
LCD_DATA01 |
LCD Display |
GPIO_B0_06 |
LCD_DATA02 |
LCD Display |
GPIO_B0_07 |
LCD_DATA03 |
LCD Display |
GPIO_B0_08 |
LCD_DATA04 |
LCD Display |
GPIO_B0_09 |
LCD_DATA05 |
LCD Display |
GPIO_B0_10 |
LCD_DATA06 |
LCD Display |
GPIO_B0_11 |
LCD_DATA07 |
LCD Display |
GPIO_B0_12 |
LCD_DATA08 |
LCD Display |
GPIO_B0_13 |
LCD_DATA09 |
LCD Display |
GPIO_B0_14 |
LCD_DATA10 |
LCD Display |
GPIO_B0_15 |
LCD_DATA11 |
LCD Display |
GPIO_B1_00 |
LCD_DATA12 |
LCD Display |
GPIO_B1_01 |
LCD_DATA13 |
LCD Display |
GPIO_B1_02 |
LCD_DATA14 |
LCD Display |
GPIO_B1_03 |
LCD_DATA15 |
LCD Display |
GPIO_B1_04 |
ENET_RX_DATA00 |
Ethernet |
GPIO_B1_05 |
ENET_RX_DATA01 |
Ethernet |
GPIO_B1_06 |
ENET_RX_EN |
Ethernet |
GPIO_B1_07 |
ENET_TX_DATA00 |
Ethernet |
GPIO_B1_08 |
ENET_TX_DATA01 |
Ethernet |
GPIO_B1_09 |
ENET_TX_EN |
Ethernet |
GPIO_B1_10 |
ENET_REF_CLK |
Ethernet |
GPIO_B1_11 |
ENET_RX_ER |
Ethernet |
GPIO_B1_12 |
GPIO |
SD Card |
GPIO_B1_14 |
USDHC1_VSELECT |
SD Card |
GPIO_B1_15 |
BACKLIGHT_CTL |
LCD Display |
GPIO_EMC_40 |
ENET_MDC |
Ethernet |
GPIO_EMC_41 |
ENET_MDIO |
Ethernet |
GPIO_AD_B0_09 |
ENET_RST |
Ethernet |
GPIO_AD_B0_10 |
ENET_INT |
Ethernet |
GPIO_SD_B0_00 |
USDHC1_CMD/LPSPI1_SCK | SD Card/SPI |
|
GPIO_SD_B0_01 |
USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI |
|
GPIO_SD_B0_02 |
USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI |
|
GPIO_SD_B0_03 |
USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI |
|
GPIO_SD_B0_04 |
USDHC1_DATA2 |
SD Card |
GPIO_SD_B0_05 |
USDHC1_DATA3 |
SD Card |
GPIO_AD_B1_02 |
1588_EVENT2_OUT |
1588 |
GPIO_AD_B1_03 |
1588_EVENT2_IN |
1588 |
Note
In order to use the SPI peripheral on this board, resistors R278, R279, R280, and R281 must be populated with zero ohm resistors
System Clock
The MIMXRT1050 SoC is configured to use SysTick as the system clock source, running at 600MHz.
When power management is enabled, the 32 KHz low frequency oscillator on the board will be used as a source for the GPT timer to generate a system clock. This clock enables lower power states, at the cost of reduced resolution
Serial Port
The MIMXRT1050 SoC has eight UARTs. LPUART1 is configured for the console,
LPUART3 for the Bluetooth Host Controller Interface (BT HCI), and the
remaining are not used.
USB
The RT1050 SoC has two USB OTG (USBOTG) controllers that supports both device and host functions through its micro USB connectors. Only USB device function is supported in Zephyr at the moment.
Board Targets
This board has two variants that can be targeted,
depending on which flash to set as zephyr,flash:
mimxrt1050_evk/mimxrt1052/hyperflashis the default variant for the out of box setup of the board using hyperflash.mimxrt1050_evk/mimxrt1052/qspiis for a board that has been reworked to use the qspi flash instead of hyperflash.
Programming and Debugging
The mimxrt1050_evk board supports the runners and associated west commands listed below.
| flash | debug | debugserver | attach | rtt | |
|---|---|---|---|---|---|
| jlink | ✅ | ✅ | ✅ | ✅ | ✅ |
| linkserver | ✅ (default) | ✅ (default) | ✅ | ✅ | |
| pyocd | ✅ | ✅ | ✅ | ✅ | ✅ |
Note
Newer revisions of this board use LPC-LINK2 Onboard Debug Probe, while older revisions use the OpenSDA Onboard Debug Probe. Schematic revisions A/A1 use the K20 OpenSDA probe, and B/B1 use the LPC-Link2 LPC4322 probe.
This board supports 3 debug host tools. Please install your preferred host tool, then follow the instructions in Configuring a Debug Probe (Schematic A/A1) or Configuring a Debug Probe (Schematic B/B1), depending on board schematic revision to configure the board appropriately.
LinkServer Debug Host Tools (Default, NXP Supported)
J-Link Debug Host Tools (NXP Supported)
pyOCD Debug Host Tools (Not supported by NXP)
Once the host tool and board are configured, build and flash applications as usual (see Building an Application and Run an Application for more details).
Configuring a Debug Probe (Schematic A/A1)
For the RT1050 Schematic Rev A, J32/J33 are the SWD isolation jumpers, SW4 is the reset button, and J21 is the 20 pin JTAG/SWD header.
A debug probe is used for both flashing and debugging the board. This board has an OpenSDA Onboard Debug Probe. The default firmware present on this probe is the OpenSDA DAPLink Onboard Debug Probe.
Based on the host tool installed, please use the following instructions to setup your debug probe:
Using DAPLink on NXP OpenSDA Boards
If the debug firmware has been modified, follow the instructions provided at OpenSDA DAPLink Onboard Debug Probe to reprogram the default debug probe firmware on this board.
Ensure the SWD isolation jumpers are populated
Using J-Link on NXP OpenSDA Boards
There are two options: the onboard debug circuit can be updated with Segger J-Link firmware, or a J-Link External Debug Probe can be attached to the board.
To update the onboard debug circuit, please do the following:
If the debug firmware has been modified, follow the instructions provided at OpenSDA J-Link Onboard Debug Probe to reprogram the default debug probe firmware on this board.
Ensure the SWD isolation jumpers are removed.
To attach an external J-Link probe, ensure the SWD isolation jumpers are removed, and connect the external probe to the JTAG/SWD header.
Configuring a Debug Probe (Schematic B/B1)
For the RT1050 Schematic Rev B, J47/J48 are the SWD isolation jumpers, J42 is the DFU mode jumper, and J21 is the 20 pin JTAG/SWD header.
A debug probe is used for both flashing and debugging the board. This board has an LPC-LINK2 Onboard Debug Probe. The default firmware present on this probe is the LPC-Link2 DAPLink Onboard Debug Probe.
Based on the host tool installed, please use the following instructions to setup your debug probe:
LinkServer Debug Host Tools: Using CMSIS-DAP with LPC-Link2 Probe
pyOCD Debug Host Tools: Using CMSIS-DAP with LPC-Link2 Probe
Using CMSIS-DAP with LPC-Link2 Probe
Follow the instructions provided at LPC-LINK2 CMSIS DAP Onboard Debug Probe to reprogram the default debug probe firmware on this board.
Ensure the SWD isolation jumpers are populated
Using J-Link with LPC-Link2 Probe
There are two options: the onboard debug circuit can be updated with Segger J-Link firmware, or a J-Link External Debug Probe can be attached to the EVK.
To update the onboard debug circuit, please do the following:
Switch the power source for the EVK to a different source than the debug USB, as the J-Link firmware does not power the EVK via the debug USB.
Follow the instructions provided at LPC-Link2 J-Link Onboard Debug Probe to reprogram the default debug probe firmware on this board.
Ensure the SWD isolation jumpers are populated.
To attach an external J-Link probe, ensure the SWD isolation jumpers are removed, then connect the probe to the external JTAG/SWD header
Configuring a Console
Regardless of your choice in debug probe, we will use the OpenSDA microcontroller as a usb-to-serial adapter for the serial console. Check that jumpers J30 and J31 are on (they are on by default when boards ship from the factory) to connect UART signals to the OpenSDA microcontroller.
Connect a USB cable from your PC to J28.
Use the following settings with your serial terminal of choice (minicom, putty, etc.):
Speed: 115200
Data: 8 bits
Parity: None
Stop bits: 1
Flashing
Here is an example for the Hello World application.
# From the root of the zephyr repository
west build -b mimxrt1050_evk//hyperflash samples/hello_world
west flash
Open a serial terminal, reset the board (press the SW4 button), and you should see the following message in the terminal:
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! mimxrt1050_evk//hyperflash
Debugging
Here is an example for the Hello World application.
# From the root of the zephyr repository
west build -b mimxrt1050_evk//hyperflash samples/hello_world
west debug
Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! mimxrt1050_evk//hyperflash
Troubleshooting
If the debug probe fails to connect with the following error, it’s possible
that the boot header in HyperFlash is invalid or corrupted. The boot header is
configured by CONFIG_NXP_IMXRT_BOOT_HEADER.
Remote debugging using :2331
Remote communication error. Target disconnected.: Connection reset by peer.
"monitor" command not supported by this target.
"monitor" command not supported by this target.
You can't do that when your target is `exec'
(gdb) Could not connect to target.
Please check power, connection and settings.
You can fix it by erasing and reprogramming the HyperFlash with the following steps:
Set the SW7 DIP switches to ON-ON-ON-OFF to prevent booting from HyperFlash.
Reset by pressing SW4
Run
west debugorwest flashagain with a known working Zephyr application.Set the SW7 DIP switches to OFF-ON-ON-OFF to boot from HyperFlash.
Reset by pressing SW4
Board Revisions
The original MIMXRT1050-EVK (rev A0) board was updated with a newer MIMXRT1050-EVKB (rev A1) board, with these major hardware differences:
SoC changed from MIMXRT1052DVL6A to MIMXRT1052DVL6B
Hardware bug fixes for: power, interfaces, and memory
Arduino headers included
For more details, please see the following NXP i.MXRT1050 A0 to A1 Migration Guide.
Current Zephyr build supports the new MIMXRT1050-EVKB
Support Resources for Zephyr
MCUXpresso for VS Code, wiki documentation and Zephyr lab guides
NXP’s Zephyr landing page (including training resources)