FRDM-MCXA156

Overview

FRDM-MCXA156 are compact and scalable development boards for rapid prototyping of MCX A144/5/6 A154/5/6 MCUs. They offer industry standard headers for easy access to the MCU’s I/Os, integrated open-standard serial interfaces, external flash memory and an on-board MCU-Link debugger. Additional tools like our Expansion Board Hub for add-on boards and the Application Code Hub for software examples are available through the MCUXpresso Developer Experience.

Hardware

  • MCX-A156 Arm Cortex-M33 microcontroller running at 96 MHz

  • 1MB dual-bank on chip Flash

  • 128 KB RAM

  • USB full-speed with on-chip FS PHY. USB Type-C connectors

  • 1x FlexCAN with FD, 1x I3Cs

  • On-board MCU-Link debugger with CMSIS-DAP

  • Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS

For more information about the MCX-A156 SoC and FRDM-MCXA156 board, see:

Supported Features

The frdm_mcxa156 board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
frdm_mcxa156
/
mcxa156

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-M33F CPU1

arm,cortex-m33f

ADC

on-chip

LPC LPADC1 1

nxp,lpc-lpadc

CAN

on-chip

NXP FlexCAN controller1

nxp,flexcan

Clock control

on-chip

LPC SYSCON & CLKCTL IP node1

nxp,lpc-syscon

Counter

on-chip

NXP MCUX Standard Timer/Counter1 4

nxp,lpc-ctimer

on-chip

NXP LPTMR1

nxp,lptmr

DAC

on-chip

NXP MCUX LPDAC1

nxp,lpdac

DMA

on-chip

NXP MCUX EDMA controller1

nxp,mcux-edma

Flash controller

on-chip

NXP MSF1 Flash Memory Module (FMU)1

nxp,msf1

GPIO & Headers

on-chip

Kinetis GPIO5

nxp,kinetis-gpio

on-board

GPIO pins exposed on NXP LCD 8080 interface (e.g., used on LCD-PAR-035 panel)1

nxp,lcd-8080

I2C

on-chip

NXP LPI2C controller2 2

nxp,lpi2c

I3C

on-chip

NXP MCUX I3C controller1

nxp,mcux-i3c

Input

on-board

Group of GPIO-bound input keys1

gpio-keys

Interrupt controller

on-chip

ARMv8-M NVIC (Nested Vectored Interrupt Controller)1

arm,v8m-nvic

LED

on-board

Group of GPIO-controlled LEDs1

gpio-leds

MIPI-DBI

on-chip

NXP FlexIO LCD controller1

nxp,mipi-dbi-flexio-lcdif

Miscellaneous

on-chip

NXP FlexIO controller1

nxp,flexio

MTD

on-chip

Flash node1

soc-nv-flash

on-board

Fixed partitions of a flash (or other non-volatile storage) memory1

fixed-partitions

Pin control

on-chip

NXP PORT Pin Controller5

nxp,port-pinmux

on-chip

NXP PORT Pin Controller1

nxp,port-pinctrl

PWM

on-chip

NXP eFLEX PWM module with mcux-pwm submodules2

nxp,flexpwm

on-chip

NXP MCUX PWM1 5

nxp,imx-pwm

Reset controller

on-chip

LPC SYSCON Peripheral reset controller1

nxp,lpc-syscon-reset

Sensors

on-board

NXP P3T1755 digital temperature sensor connected to I2C bus1

nxp,p3t1755

on-chip

NXP low-power analog comparator (LPCMP)1 1

nxp,lpcmp

Serial controller

on-chip

NXP LPUART2

nxp,lpuart

SPI

on-chip

NXP LPSPI controller1 1

nxp,lpspi

SRAM

on-chip

Generic on-chip SRAM2

mmio-sram

Timer

on-chip

ARMv8-M System Tick1

arm,armv8m-systick

USB

on-chip

NPX Kinetis USBFSOTG Controller in device mode1

nxp,kinetis-usbd

Watchdog

on-chip

LPC Windowed Watchdog Timer1

nxp,lpc-wwdt

Connections and IOs

The MCX-A156 SoC has 5 gpio controllers and has pinmux registers which can be used to configure the functionality of a pin.

Name

Function

Usage

PIO0_2

UART

UART RX

PIO0_3

UART

UART TX

System Clock

The MCX-A156 SoC is configured to use FRO running at 96MHz as a source for the system clock.

Serial Port

The FRDM-MCXA156 SoC has 5 LPUART interfaces for serial communication. LPUART 0 is configured as UART for the console.

Programming and Debugging

The frdm_mcxa156 board supports the runners and associated west commands listed below.

flash debug attach debugserver rtt
jlink
linkserver ✅ (default) ✅ (default)
pyocd

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.

Using LinkServer

Linkserver is the default runner for this board, and supports the factory default MCU-Link firmware. Follow the instructions in MCU-Link CMSIS-DAP Onboard Debug Probe to reprogram the default MCU-Link firmware. This only needs to be done if the default onboard debug circuit firmware was changed. To put the board in DFU mode to program the firmware, short jumper JP5.

Configuring a Console

Connect a USB cable from your PC to J21, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:

  • Speed: 115200

  • Data: 8 bits

  • Parity: None

  • Stop bits: 1

Flashing

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxa156 samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:

*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxa156/mcxa156

Debugging

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxa156/mcxa156 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxa156/mcxa156

Troubleshooting

Using Segger SystemView and RTT

Note that when using SEGGER SystemView or RTT with this SOC, the RTT control block address must be set manually within SystemView or the RTT Viewer. The address provided to the tool should be the location of the _SEGGER_RTT symbol, which can be found using a debugger or by examining the zephyr.map file output by the linker.

The RTT control block address must be provided manually because this SOC supports ECC RAM. If the SEGGER tooling searches the ECC RAM space for the control block a fault will occur, provided that ECC is enabled and the RAM segment being searched has not been initialized to a known value.

Support Resources for Zephyr