FRDM-MCXN947
Overview
FRDM-MCXN947 are compact and scalable development boards for rapid prototyping of MCX N94 and N54 MCUs. They offer industry standard headers for easy access to the MCUs I/Os, integrated open-standard serial interfaces, external flash memory and an on-board MCU-Link debugger. MCX N Series are high-performance, low-power microcontrollers with intelligent peripherals and accelerators providing multi-tasking capabilities and performance efficiency.
Hardware
MCX-N947 Dual Arm Cortex-M33 microcontroller running at 150 MHz
2MB dual-bank on chip Flash
512 KB RAM
External Quad SPI flash over FlexSPI
USB high-speed (Host/Device) with on-chip HS PHY. HS USB Type-C connectors
10x LP Flexcomms each supporting SPI, I2C, UART
2x FlexCAN with FD, 2x I3Cs, 2x SAI
1x Ethernet with QoS
On-board MCU-Link debugger with CMSIS-DAP
Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS
For more information about the MCX-N947 SoC and FRDM-MCXN947 board, see:
Supported Features
The frdm_mcxn947 board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M33F CPU1 |
|
ADC |
on-chip |
||
CAN |
on-chip |
||
Clock control |
on-chip |
LPC SYSCON & CLKCTL IP node1 |
|
Counter |
on-chip |
||
on-chip |
NXP LPTMR2 |
||
on-chip |
NXP Multirate Timer1 |
||
on-chip |
|||
DAC |
on-chip |
||
DMA |
on-chip |
||
on-chip |
NXP SmartDMA controller1 |
||
Ethernet |
on-chip |
NXP ENET QOS IP Module1 |
|
on-chip |
NXP ENET QOS MAC1 |
||
on-board |
Generic MII PHY1 |
||
Flash controller |
on-chip |
NXP MSF1 Flash Memory Module (FMU)1 |
|
GPIO & Headers |
on-chip |
||
on-board |
GPIO pins exposed on NXP LCD 8080 interface (e.g., used on LCD-PAR-035 panel)1 |
||
Hardware information |
on-chip |
NXP LPC 128-bit Unique identifier1 |
|
I2C |
on-chip |
||
I2S |
on-chip |
NXP mcux SAI-I2S controller2 |
|
I3C |
on-chip |
||
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
Mailbox |
on-chip |
NXP Mailbox Unit as Zephyr MBOX1 |
|
MDIO |
on-chip |
NXP ENET QOS MDIO Controller1 |
|
Multi-Function Device |
on-chip |
||
MIPI-DBI |
on-chip |
NXP FlexIO LCD controller1 |
|
Miscellaneous |
on-chip |
NXP FlexIO controller1 |
|
MMU / MPU |
on-chip |
ARMv8-M MPU (Memory Protection Unit)1 |
|
MTD |
on-chip |
Flash node1 |
|
on-board |
Fixed partitions of a flash (or other non-volatile storage) memory2 |
||
on-board |
NXP FlexSPI NOR1 |
||
Pin control |
on-chip |
NXP PORT Pin Controller6 |
|
on-chip |
NXP PORT Pin Controller1 |
||
PWM |
on-chip |
NXP eFLEX PWM module with mcux-pwm submodules2 |
|
on-chip |
|||
on-chip |
NXP SCTimer PWM1 |
||
Regulator |
on-chip |
NXP VREF SOC peripheral1 |
|
Reset controller |
on-chip |
LPC SYSCON Peripheral reset controller1 |
|
RTC |
on-chip |
IRTC1 |
|
SDHC |
on-chip |
NXP imx USDHC controller1 |
|
Sensors |
on-chip |
||
Serial controller |
on-chip |
||
SPI |
on-chip |
||
on-chip |
NXP FlexSPI controller1 |
||
SRAM |
on-chip |
Generic on-chip SRAM3 |
|
Timer |
on-chip |
ARMv8-M System Tick1 |
|
on-chip |
NXP OS Timer on i.MX-RT5xx/6xx1 |
||
USB |
on-chip |
NPX Kinetis USBFSOTG Controller in device mode1 |
|
on-chip |
NXP EHCI USB device mode1 |
||
on-chip |
NXP USB high speed phy that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis platforms if high speed usb is supported on these platforms1 |
||
Video |
on-board |
OV7670 CMOS video sensor1 |
|
on-board |
NXP SmartDMA Video Driver1 |
||
Watchdog |
on-chip |
LPC Windowed Watchdog Timer1 |
Dual Core samples
Core |
Boot Address |
Comment |
|---|---|---|
CPU0 |
0x10000000[1856K] |
primary core flash |
CPU1 |
0x101d0000[192K] |
secondary core flash |
Memory |
Address[Size] |
Comment |
|---|---|---|
srama |
0x20000000[320k] |
CPU0 ram |
sramg |
0x20050000[64k] |
CPU1 ram |
sramh |
0x20060000[32k] |
Shared memory |
Targets available
The default configuration file boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig only enables the first core. CPU0 is the only target that can run standalone.
CPU1 does not work without CPU0 enabling it.
To enable CPU1, create System Build application project and enable the
second core with config CONFIG_SECOND_CORE_MCUX.
Please have a look at some already enabled samples:
Connections and IOs
The MCX-N947 SoC has 6 gpio controllers and has pinmux registers which can be used to configure the functionality of a pin.
Name |
Function |
Usage |
|---|---|---|
P0_PIO1_8 |
UART |
UART RX cpu0 |
P1_PIO1_9 |
UART |
UART TX cpu0 |
P4_PIO4_3 |
UART |
UART RX cpu1 |
P4_PIO4_2 |
UART |
UART TX cpu1 |
System Clock
The MCX-N947 SoC is configured to use PLL0 running at 150MHz as a source for the system clock.
Serial Port
The FRDM-MCXN947 SoC has 10 FLEXCOMM interfaces for serial communication. Flexcomm 4 is configured as UART for the console.
Programming and Debugging
The frdm_mcxn947 board supports the runners and associated west commands listed below.
| flash | debug | debugserver | attach | rtt | |
|---|---|---|---|---|---|
| jlink | ✅ | ✅ | ✅ | ✅ | ✅ |
| linkserver | ✅ (default) | ✅ (default) | ✅ | ✅ | |
| pyocd | ✅ | ✅ | ✅ | ✅ | ✅ |
Build and flash applications as usual (see Building an Application and Run an Application for more details).
Configuring a Debug Probe
A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
Using LinkServer
Linkserver is the default runner for this board, and supports the factory
default MCU-Link firmware. Follow the instructions in
MCU-Link CMSIS-DAP Onboard Debug Probe to reprogram the default MCU-Link
firmware. This only needs to be done if the default onboard debug circuit
firmware was changed. To put the board in DFU mode to program the firmware,
short jumper J21.
Using J-Link
There are two options. The onboard debug circuit can be updated with Segger
J-Link firmware by following the instructions in
MCU-Link JLink Onboard Debug Probe.
To be able to program the firmware, you need to put the board in DFU mode
by shortening the jumper J21.
The second option is to attach a J-Link External Debug Probe to the
10-pin SWD connector (J23) of the board. Additionally, the jumper J19 must
be shortened.
For both options use the -r jlink option with west to use the jlink runner.
west flash -r jlink
Configuring a Console
Connect a USB cable from your PC to J17, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:
Speed: 115200
Data: 8 bits
Parity: None
Stop bits: 1
Flashing
Here is an example for the Hello World application.
# From the root of the zephyr repository
west build -b frdm_mcxn947/mcxn947/cpu0 samples/hello_world
west flash
Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:
*** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 ***
Hello World! frdm_mcxn947/mcxn947/cpu0
Building a dual-core image
The dual-core samples are run using frdm_mcxn947/mcxn947/cpu0 target.
Images built for frdm_mcxn947/mcxn947/cpu1 will be loaded from flash
and executed on the second core when CONFIG_SECOND_CORE_MCUX is selected.
For an example of building for both cores with System Build, see samples/subsys/ipc/ipc_service/static_vrings
Here is an example for the MBOX Data application.
west build -b frdm_mcxn947/mcxn947/cpu0 --sysbuild zephyr/samples/drivers/mbox_data
west flash
Flashing to QSPI
Here is an example for the Hello World application.
west build -b frdm_mcxn947/mcxn947/cpu0/qspi zephyr/samples/hello_world -- -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"bootloader/mcuboot/root-rsa-2048.pem\" -DCONFIG_BOOTLOADER_MCUBOOT=y
west flash
In order to load Zephyr application from QSPI you should program a bootloader like MCUboot bootloader to internal flash. Here are the steps.
west build -b frdm_mcxn947/mcxn947/cpu0/qspi bootloader/mcuboot/boot/zephyr
west flash
Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:
*** Booting MCUboot v2.1.0-rc1-2-g9f034729d99a ***
*** Using Zephyr OS build v3.6.0-4046-gf279a03af8ab ***
I: Starting bootloader
I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Boot source: none
I: Image index: 0, Swap type: none
I: Bootloader chainload address offset: 0x0
I: Jumping to the first image slot
*** Booting Zephyr OS build v3.6.0-4046-gf279a03af8ab ***
Hello World! frdm_mcxn947/mcxn947/cpu0/qspi
Debugging
Here is an example for the Hello World application.
# From the root of the zephyr repository
west build -b frdm_mcxn947/mcxn947/cpu0 samples/hello_world
west debug
Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:
*** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 ***
Hello World! frdm_mcxn947/mcxn947/cpu0
Debugging a dual-core image
For dual core builds, the secondary core should be placed into a loop, then a debugger can be attached. As a reference please see (AN13264, section 4.2.3 for more information). The reference is for the RT1170 but similar technique can be also used here.
Troubleshooting
Using Segger SystemView and RTT
Note that when using SEGGER SystemView or RTT with this SOC, the RTT control
block address must be set manually within SystemView or the RTT Viewer. The
address provided to the tool should be the location of the _SEGGER_RTT
symbol, which can be found using a debugger or by examining the zephyr.map
file output by the linker.
The RTT control block address must be provided manually because this SOC supports ECC RAM. If the SEGGER tooling searches the ECC RAM space for the control block a fault will occur, provided that ECC is enabled and the RAM segment being searched has not been initialized to a known value.
Support Resources for Zephyr
MCUXpresso for VS Code, wiki documentation and Zephyr lab guides
NXP’s Zephyr landing page (including training resources)