FRDM-MCXN947

Board Overview

FRDM-MCXN947

Name:

frdm_mcxn947

Vendor:

NXP Semiconductors

Architecture:

arm

SoC:

mcxn947

Browse board sources

Overview

FRDM-MCXN947 are compact and scalable development boards for rapid prototyping of MCX N94 and N54 MCUs. They offer industry standard headers for easy access to the MCUs I/Os, integrated open-standard serial interfaces, external flash memory and an on-board MCU-Link debugger. MCX N Series are high-performance, low-power microcontrollers with intelligent peripherals and accelerators providing multi-tasking capabilities and performance efficiency.

Hardware

• MCX-N947 Dual Arm Cortex-M33 microcontroller running at 150 MHz

• 2MB dual-bank on chip Flash

• 512 KB RAM

• External Quad SPI flash over FlexSPI

• USB high-speed (Host/Device) with on-chip HS PHY. HS USB Type-C connectors

• 10x LP Flexcomms each supporting SPI, I2C, UART

• 2x FlexCAN with FD, 2x I3Cs, 2x SAI

• 1x Ethernet with QoS

• On-board MCU-Link debugger with CMSIS-DAP

• Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS

For more information about the MCX-N947 SoC and FRDM-MCXN947 board, see:

• MCX-N947 SoC Website

• MCX-N947 Datasheet

• MCX-N947 Reference Manual

• FRDM-MCXN947 Website

• FRDM-MCXN947 User Guide

• FRDM-MCXN947 Board User Manual

• FRDM-MCXN947 Schematics

Supported Features

The frdm_mcxn947 board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

frdm_mcxn947

/

mcxn947/cpu0mcxn947/cpu0/qspimcxn947/cpu1

frdm_mcxn947/mcxn947/cpu0 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33F CPU1	arm,cortex-m33f
ADC	on-chip	LPC LPADC1 1	nxp,lpc-lpadc
CAN	on-chip	NXP FlexCAN controller1 1	nxp,flexcan
Clock control	on-chip	LPC SYSCON & CLKCTL IP node1	nxp,lpc-syscon
Counter	on-chip	NXP MCUX Standard Timer/Counter1 4	nxp,lpc-ctimer
	on-chip	NXP LPTMR2	nxp,lptmr
	on-chip	NXP Multirate Timer1	nxp,mrt
	on-chip	NXP Multirate Timer Channel1 3	nxp,mrt-channel
DAC	on-chip	NXP MCUX LPDAC1 1	nxp,lpdac
DMA	on-chip	NXP MCUX EDMA controller1 1	nxp,mcux-edma
	on-chip	NXP SmartDMA controller1	nxp,smartdma
Ethernet	on-chip	NXP ENET QOS IP Module1	nxp,enet-qos
	on-chip	NXP ENET QOS MAC1	nxp,enet-qos-mac
	on-board	Generic MII PHY1	ethernet-phy
Flash controller	on-chip	NXP MSF1 Flash Memory Module (FMU)1	nxp,msf1
GPIO & Headers	on-chip	Kinetis GPIO4 2	nxp,kinetis-gpio
	on-board	GPIO pins exposed on NXP LCD 8080 interface (e.g., used on LCD-PAR-035 panel)1	nxp,lcd-8080
	on-board	ArduCam 20-pin header camera connector.1	arducam,dvp-20pin-connector
Hardware information	on-chip	NXP LPC 128-bit Unique identifier1	nxp,lpc-uid
I2C	on-chip	NXP LPI2C controller2 8	nxp,lpi2c
I2S	on-chip	NXP mcux SAI-I2S controller2	nxp,mcux-i2s
I3C	on-chip	NXP MCUX I3C controller1 1	nxp,mcux-i3c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8m-nvic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
Mailbox	on-chip	NXP Mailbox Unit as Zephyr MBOX1	nxp,mbox-mailbox
MDIO	on-chip	NXP ENET QOS MDIO Controller1	nxp,enet-qos-mdio
Multi-Function Device	on-chip	Low Power Flexcomm4 6	nxp,lp-flexcomm
MIPI-DBI	on-chip	NXP FlexIO LCD controller1	nxp,mipi-dbi-flexio-lcdif
Miscellaneous	on-chip	NXP FlexIO controller1	nxp,flexio
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	arm,armv8m-mpu
MTD	on-chip	Flash node1	soc-nv-flash
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory2	fixed-partitions
	on-board	NXP FlexSPI NOR1	nxp,imx-flexspi-nor
Pin control	on-chip	NXP PORT Pin Controller6	nxp,port-pinmux
	on-chip	NXP PORT Pin Controller1	nxp,port-pinctrl
PWM	on-chip	NXP eFLEX PWM module with mcux-pwm submodules2	nxp,flexpwm
	on-chip	NXP MCUX PWM1 7	nxp,imx-pwm
	on-chip	NXP SCTimer PWM1	nxp,sctimer-pwm
Regulator	on-chip	NXP VREF SOC peripheral1	nxp,vref
Reset controller	on-chip	LPC SYSCON Peripheral reset controller1	nxp,lpc-syscon-reset
RTC	on-chip	IRTC1	nxp,irtc
SDHC	on-chip	NXP imx USDHC controller1	nxp,imx-usdhc
Sensors	on-chip	NXP low-power analog comparator (LPCMP)1 2	nxp,lpcmp
Serial controller	on-chip	NXP LPUART2 8	nxp,lpuart
SPI	on-chip	NXP LPSPI controller1 9	nxp,lpspi
	on-chip	NXP FlexSPI controller1	nxp,imx-flexspi
SRAM	on-chip	Generic on-chip SRAM3	mmio-sram
Timer	on-chip	ARMv8-M System Tick1	arm,armv8m-systick
	on-chip	NXP OS Timer on i.MX-RT5xx/6xx1	nxp,os-timer
USB	on-chip	NPX Kinetis USBFSOTG Controller in device mode1	nxp,kinetis-usbd
	on-chip	NXP EHCI USB device mode1	nxp,ehci
	on-chip	NXP USB High Speed PHY1	nxp,usbphy
Video	on-board	NXP SmartDMA Video Driver1	nxp,video-smartdma
Watchdog	on-chip	LPC Windowed Watchdog Timer1	nxp,lpc-wwdt

frdm_mcxn947/mcxn947/cpu0/qspi target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33F CPU1	arm,cortex-m33f
ADC	on-chip	LPC LPADC1 1	nxp,lpc-lpadc
CAN	on-chip	NXP FlexCAN controller1 1	nxp,flexcan
Clock control	on-chip	LPC SYSCON & CLKCTL IP node1	nxp,lpc-syscon
Counter	on-chip	NXP MCUX Standard Timer/Counter1 4	nxp,lpc-ctimer
	on-chip	NXP LPTMR2	nxp,lptmr
	on-chip	NXP Multirate Timer1	nxp,mrt
	on-chip	NXP Multirate Timer Channel1 3	nxp,mrt-channel
DAC	on-chip	NXP MCUX LPDAC1 1	nxp,lpdac
DMA	on-chip	NXP MCUX EDMA controller1 1	nxp,mcux-edma
	on-chip	NXP SmartDMA controller1	nxp,smartdma
Ethernet	on-chip	NXP ENET QOS IP Module1	nxp,enet-qos
	on-chip	NXP ENET QOS MAC1	nxp,enet-qos-mac
	on-board	Generic MII PHY1	ethernet-phy
Flash controller	on-chip	NXP MSF1 Flash Memory Module (FMU)1	nxp,msf1
GPIO & Headers	on-chip	Kinetis GPIO4 2	nxp,kinetis-gpio
	on-board	GPIO pins exposed on NXP LCD 8080 interface (e.g., used on LCD-PAR-035 panel)1	nxp,lcd-8080
	on-board	ArduCam 20-pin header camera connector.1	arducam,dvp-20pin-connector
Hardware information	on-chip	NXP LPC 128-bit Unique identifier1	nxp,lpc-uid
I2C	on-chip	NXP LPI2C controller2 8	nxp,lpi2c
I2S	on-chip	NXP mcux SAI-I2S controller2	nxp,mcux-i2s
I3C	on-chip	NXP MCUX I3C controller1 1	nxp,mcux-i3c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8m-nvic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
Mailbox	on-chip	NXP Mailbox Unit as Zephyr MBOX1	nxp,mbox-mailbox
MDIO	on-chip	NXP ENET QOS MDIO Controller1	nxp,enet-qos-mdio
Multi-Function Device	on-chip	Low Power Flexcomm4 6	nxp,lp-flexcomm
MIPI-DBI	on-chip	NXP FlexIO LCD controller1	nxp,mipi-dbi-flexio-lcdif
Miscellaneous	on-chip	NXP FlexIO controller1	nxp,flexio
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	arm,armv8m-mpu
MTD	on-chip	Flash node1	soc-nv-flash
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory2	fixed-partitions
	on-board	NXP FlexSPI NOR1	nxp,imx-flexspi-nor
Pin control	on-chip	NXP PORT Pin Controller6	nxp,port-pinmux
	on-chip	NXP PORT Pin Controller1	nxp,port-pinctrl
PWM	on-chip	NXP eFLEX PWM module with mcux-pwm submodules2	nxp,flexpwm
	on-chip	NXP MCUX PWM1 7	nxp,imx-pwm
	on-chip	NXP SCTimer PWM1	nxp,sctimer-pwm
Regulator	on-chip	NXP VREF SOC peripheral1	nxp,vref
Reset controller	on-chip	LPC SYSCON Peripheral reset controller1	nxp,lpc-syscon-reset
RTC	on-chip	IRTC1	nxp,irtc
SDHC	on-chip	NXP imx USDHC controller1	nxp,imx-usdhc
Sensors	on-chip	NXP low-power analog comparator (LPCMP)1 2	nxp,lpcmp
Serial controller	on-chip	NXP LPUART2 8	nxp,lpuart
SPI	on-chip	NXP LPSPI controller1 9	nxp,lpspi
	on-chip	NXP FlexSPI controller1	nxp,imx-flexspi
SRAM	on-chip	Generic on-chip SRAM3	mmio-sram
Timer	on-chip	ARMv8-M System Tick1	arm,armv8m-systick
	on-chip	NXP OS Timer on i.MX-RT5xx/6xx1	nxp,os-timer
USB	on-chip	NPX Kinetis USBFSOTG Controller in device mode1	nxp,kinetis-usbd
	on-chip	NXP EHCI USB device mode1	nxp,ehci
	on-chip	NXP USB High Speed PHY1	nxp,usbphy
Video	on-board	NXP SmartDMA Video Driver1	nxp,video-smartdma
Watchdog	on-chip	LPC Windowed Watchdog Timer1	nxp,lpc-wwdt

frdm_mcxn947/mcxn947/cpu1 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33 CPU1	arm,cortex-m33
ADC	on-chip	LPC LPADC2	nxp,lpc-lpadc
CAN	on-chip	NXP FlexCAN controller2	nxp,flexcan
Clock control	on-chip	LPC SYSCON & CLKCTL IP node1	nxp,lpc-syscon
Counter	on-chip	NXP MCUX Standard Timer/Counter5	nxp,lpc-ctimer
	on-chip	NXP LPTMR2	nxp,lptmr
	on-chip	NXP Multirate Timer1	nxp,mrt
	on-chip	NXP Multirate Timer Channel4	nxp,mrt-channel
DAC	on-chip	NXP MCUX LPDAC2	nxp,lpdac
DMA	on-chip	NXP MCUX EDMA controller1 1	nxp,mcux-edma
	on-chip	NXP SmartDMA controller1	nxp,smartdma
Ethernet	on-chip	NXP ENET QOS IP Module1	nxp,enet-qos
	on-chip	NXP ENET QOS MAC1	nxp,enet-qos-mac
	on-board	Generic MII PHY1	ethernet-phy
Flash controller	on-chip	NXP MSF1 Flash Memory Module (FMU)1	nxp,msf1
GPIO & Headers	on-chip	Kinetis GPIO4 2	nxp,kinetis-gpio
	on-board	GPIO pins exposed on NXP LCD 8080 interface (e.g., used on LCD-PAR-035 panel)1	nxp,lcd-8080
	on-board	ArduCam 20-pin header camera connector.1	arducam,dvp-20pin-connector
Hardware information	on-chip	NXP LPC 128-bit Unique identifier1	nxp,lpc-uid
I2C	on-chip	NXP LPI2C controller10	nxp,lpi2c
I2S	on-chip	NXP mcux SAI-I2S controller2	nxp,mcux-i2s
I3C	on-chip	NXP MCUX I3C controller2	nxp,mcux-i3c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8m-nvic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
Mailbox	on-chip	NXP Mailbox Unit as Zephyr MBOX1	nxp,mbox-mailbox
MDIO	on-chip	NXP ENET QOS MDIO Controller1	nxp,enet-qos-mdio
Multi-Function Device	on-chip	Low Power Flexcomm1 9	nxp,lp-flexcomm
MIPI-DBI	on-chip	NXP FlexIO LCD controller1	nxp,mipi-dbi-flexio-lcdif
Miscellaneous	on-chip	NXP FlexIO controller1	nxp,flexio
MTD	on-chip	Flash node1	soc-nv-flash
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	fixed-partitions
	on-board	NXP FlexSPI NOR1	nxp,imx-flexspi-nor
Pin control	on-chip	NXP PORT Pin Controller6	nxp,port-pinmux
	on-chip	NXP PORT Pin Controller1	nxp,port-pinctrl
PWM	on-chip	NXP eFLEX PWM module with mcux-pwm submodules2	nxp,flexpwm
	on-chip	NXP MCUX PWM8	nxp,imx-pwm
	on-chip	NXP SCTimer PWM1	nxp,sctimer-pwm
Regulator	on-chip	NXP VREF SOC peripheral1	nxp,vref
Reset controller	on-chip	LPC SYSCON Peripheral reset controller1	nxp,lpc-syscon-reset
RTC	on-chip	IRTC1	nxp,irtc
SDHC	on-chip	NXP imx USDHC controller1	nxp,imx-usdhc
Sensors	on-chip	NXP low-power analog comparator (LPCMP)3	nxp,lpcmp
Serial controller	on-chip	NXP LPUART1 9	nxp,lpuart
SPI	on-chip	NXP LPSPI controller10	nxp,lpspi
	on-chip	NXP FlexSPI controller1	nxp,imx-flexspi
SRAM	on-chip	Generic on-chip SRAM3	mmio-sram
Timer	on-chip	ARMv8-M System Tick1	arm,armv8m-systick
	on-chip	NXP OS Timer on i.MX-RT5xx/6xx1	nxp,os-timer
USB	on-chip	NPX Kinetis USBFSOTG Controller in device mode1	nxp,kinetis-usbd
	on-chip	NXP EHCI USB device mode1	nxp,ehci
	on-chip	NXP USB High Speed PHY1	nxp,usbphy
Video	on-board	NXP SmartDMA Video Driver1	nxp,video-smartdma
Watchdog	on-chip	LPC Windowed Watchdog Timer1	nxp,lpc-wwdt

Dual Core samples

Core	Flash Region	Comment
CPU0	Full flash memory (including partition slot0_partition)	Primary core with bootloader access and application in slot0_partition
CPU1	slot1_partition only	Secondary core restricted to its dedicated partition

Memory	Region	Comment
srama	RAM (320KB)	CPU0 ram
sramg	RAM (64KB)	CPU1 ram
sramh	RAM (32KB)	Shared memory

Note

The actual memory addresses are defined in the device tree and can be viewed in the generated map files after building. CPU0 accesses the full flash memory starting from its base address, while CPU1 is restricted to the slot1_partition region.

Targets available

The default configuration file boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig only enables the first core. CPU0 is the only target that can run standalone.

CPU1 does not work without CPU0 enabling it.

To enable CPU1, create System Build application project and enable the second core with config CONFIG_SECOND_CORE_MCUX.

Please have a look at some already enabled samples:

• samples/subsys/ipc/ipc_service/static_vrings

• samples/subsys/ipc/openamp

• samples/drivers/mbox

• samples/drivers/mbox_data

Connections and IOs

The MCX-N947 SoC has 6 gpio controllers and has pinmux registers which can be used to configure the functionality of a pin.

Name	Function	Usage
P0_PIO1_8	UART	UART RX cpu0
P1_PIO1_9	UART	UART TX cpu0
P4_PIO4_3	UART	UART RX cpu1
P4_PIO4_2	UART	UART TX cpu1

System Clock

The MCX-N947 SoC is configured to use PLL0 running at 150MHz as a source for the system clock.

Serial Port

The FRDM-MCXN947 SoC has 10 FLEXCOMM interfaces for serial communication. Flexcomm 4 is configured as UART for the console.

Programming and Debugging

The frdm_mcxn947 board supports the runners and associated west commands listed below.

	flash	debug	attach	debugserver	rtt
jlink	✅	✅	✅	✅	✅
linkserver	✅ (default)	✅ (default)	✅	✅
pyocd	✅	✅	✅	✅	✅

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.

Using LinkServer

Linkserver is the default runner for this board, and supports the factory default MCU-Link firmware. Follow the instructions in MCU-Link CMSIS-DAP Onboard Debug Probe to reprogram the default MCU-Link firmware. This only needs to be done if the default onboard debug circuit firmware was changed. To put the board in DFU mode to program the firmware, short jumper J21.

Using J-Link

There are two options. The onboard debug circuit can be updated with Segger J-Link firmware by following the instructions in MCU-Link JLink Onboard Debug Probe. To be able to program the firmware, you need to put the board in DFU mode by shortening the jumper J21. The second option is to attach a J-Link External Debug Probe to the 10-pin SWD connector (J23) of the board. Additionally, the jumper J19 must be shortened. For both options use the -r jlink option with west to use the jlink runner.

west flash -r jlink

Configuring a Console

Connect a USB cable from your PC to J17, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:

• Speed: 115200

• Data: 8 bits

• Parity: None

• Stop bits: 1

Flashing

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxn947/mcxn947/cpu0 samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:

*** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 ***
Hello World! frdm_mcxn947/mcxn947/cpu0

Building a dual-core image

The dual-core samples are run using frdm_mcxn947/mcxn947/cpu0 target.

Images built for frdm_mcxn947/mcxn947/cpu1 will be loaded from flash and executed on the second core when CONFIG_SECOND_CORE_MCUX is selected.

For an example of building for both cores with System Build, see samples/subsys/ipc/ipc_service/static_vrings

Here is an example for the MBOX Data application.

west build -b frdm_mcxn947/mcxn947/cpu0 --sysbuild zephyr/samples/drivers/mbox_data
west flash

Debugging

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxn947/mcxn947/cpu0 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

*** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 ***
Hello World! frdm_mcxn947/mcxn947/cpu0

Debugging a dual-core image

For dual core builds, the secondary core should be placed into a loop, then a debugger can be attached. As a reference please see (AN13264, section 4.2.3 for more information). The reference is for the RT1170 but similar technique can be also used here.

Using QSPI board variant

The FRDM-MCXN947 board includes an external QSPI flash. The MCXN947 can boot and XIP directly from this flash using the FlexSPI interface. The QSPI variant enables building applications and code to execute from the QSPI.

Programming the ROM bootloader for external QSPI

By default, the MCXN947 bootloader in ROM will boot using internal flash. But the MCU can be programmed to boot from external memory on the FlexSPI interface. Before using the QSPI board variant, the board should be programmed to boot from QSPI using the steps below.

To configure the ROM bootloader, the Protected Flash Region (PFR) must be programmed. Programming the PFR is done using NXP’s ROM bootloader tools. Some simple steps are provided in NXP’s MCUXpresso SDK example hello_world_qspi_xip readme. The binary to program with blhost is found at bootfromflexspi.bin. A much more detailed explanation is available at this post Running code from external memory with MCX N94x. The steps below program the FRDM-MCXN947 board. Note that these steps interface to the ROM bootloader through the UART serial port, but USB is another option.

1. Disconnect any terminal from the UART serial port, since these steps use that serial port.

2. Connect a USB Type-C cable to the host computer and J17 on the board, in the upper left corner. This powers the board, connects the debug probe, and connects the UART serial port used for the blhost command.

3. Place the MCU in ISP mode. On the FRDM-MCXN947 board, the ISP button can be used for this. Press and hold the ISP button SW3, on the bottom right corner of the board. Press and release the Reset button SW1 on the upper left corner of the board. The MCU has booted into ISP mode. Release the ISP button.

4. Run the blhost command:

UbuntuWindows

This step assumes the MCU serial port is connected to /dev/ttyACM0

blhost -t 2000 -p /dev/ttyACM0,115200 -j -- write-memory 0x01004000 bootfromflexspi.bin

Successful programming should look something like this:

$ blhost -t 2000 -p /dev/ttyACM0,115200 -j -- write-memory 0x01004000 bootfromflexspi.bin
{
   "command": "write-memory",
   "response": [
      256
   ],
   "status": {
      "description": "0 (0x0) Success.",
      "value": 0
   }
}

5. Reset the board with SW1 to exit ISP mode. Now the MCU is ready to boot from QSPI.

The ROM bootloader can be configured to boot from internal flash again. Repeat the steps above to program the PFR, and program the file bootfromflash.bin.

Build, flash, and debug with the QSPI variant

Once the PFR is programmed to boot from QSPI, the normal Zephyr steps to build, flash, and debug can be used with the QSPI board variant. Here are some examples.

Here is an example for the Hello World application:

west build -b frdm_mcxn947//cpu0/qspi zephyr/samples/hello_world
west flash

MCUboot can also be used with the QSPI variant. By default, this places the MCUboot bootloader in the boot-partition in QSPI flash, with the application images. The ROM bootloader will boot first and load MCUboot in the QSPI, which will load the app. This example builds and loads the Blinky sample with MCUboot using Sysbuild:

west build -b frdm_mcxn947//cpu0/qspi --sysbuild zephyr/samples/basic/blinky -- -DSB_CONFIG_BOOTLOADER_MCUBOOT=y
west flash

Open a serial terminal, reset the board with the SW1 button, and the console will print:

*** Booting MCUboot vX.Y.Z ***
*** Using Zephyr OS build vX.Y.Z ***
I: Starting bootloader
I: Image index: 0, Swap type: none
I: Bootloader chainload address offset: 0x14000
I: Image version: v0.0.0
I: Jumping to the first image slot
*** Booting Zephyr OS build vX.Y.Z ***
LED state: OFF
LED state: ON

Troubleshooting

Using Segger SystemView and RTT

Note that when using SEGGER SystemView or RTT with this SOC, the RTT control block address must be set manually within SystemView or the RTT Viewer. The address provided to the tool should be the location of the _SEGGER_RTT symbol, which can be found using a debugger or by examining the zephyr.map file output by the linker.

The RTT control block address must be provided manually because this SOC supports ECC RAM. If the SEGGER tooling searches the ECC RAM space for the control block a fault will occur, provided that ECC is enabled and the RAM segment being searched has not been initialized to a known value.

Support Resources for Zephyr

• NXP Zephyr Downstream Software Development Kit

• MCUXpresso for VS Code, wiki documentation and Zephyr lab guides

• NXP Zephyr Knowledge Hub

• NXP’s Zephyr landing page (including training resources)

• NXP Support Community forum for Zephyr