MIMXRT700-EVK

Board Overview

Name:

mimxrt700_evk

Vendor:

NXP Semiconductors

Architecture:

arm, xtensa

SoC:

mimxrt798s

Browse board sources

Overview

The new i.MX RT700 CPU architecture is composed of a high-performance main-compute subsystem, a secondary “always-on” sense-compute subsystem and specialized coprocessors.

The main-compute subsystem has a primary Arm® Cortex®-M33 running at 325 MHz, with an integrated Cadence® Tensilica® HiFi 4 DSP for more demanding DSP and audio processing tasks. The sense-compute subsystem has a second Arm® Cortex®-M33 and an integrated Cadence® Tensilica® HiFi 1 DSP. This removes the need for an external sensor hub, reducing system design complexity, footprint and BOM costs.

The HiFi4 is a high performance DSP core based upon a Very Long Instruction Word (VLIW) architecture, which is capable of processing up to eight 32x16 MACs per instruction cycle. It can be used for offloading high-performance numerical tasks such as audio and image processing and supports both fixed-point and floating-point operations.

The i.MX RT700 also features NXP’s eIQ Neutron NPU, enabled with the eIQ machine learning software development environment.

Hardware

• Main Compute Subsystem:

  • Arm Cortex-M33 up to 325 MHz

  • HiFi 4 DSP up to 325 MHz

  • eIQ Neutron NPU up to 325 MHz

• Sense Compute Subsystem:

  • Arm Cortex-M33 up to 250 MHz

  • HiFi 1 DSP up to 250 MHz

• 7.5 MB on-chip SRAM

• Three xSPI interfaces for off-chip memory expansion, supporting up to 16b wide external memories up to 250 MHz DDR

• eUSB support with integrated PHY

• Two SD/eMMC memory card interfaces—one supporting eMMC 5.0 with HS400/DDR operation

• USB high-speed host/device controller with on-chip PHY

• A digital microphone interface supporting up to 8 channels

• Serial peripherals (UART/I²C/I3C/SPI/HSPI/SAI)

• 2.5D GPU with vector graphics acceleration and frame buffer compression

• EZH-V using RISC-V core with additional SIMD/DSP instructions

• Full openVG 1.1 support

• Up to 720p@60FPS from on-chip SRAM

• LCD Interface + MIPI DSI

• Integrated JPEG and PNG support

• CSI 8/10/16-bit parallel (via FlexIO)

For more information about the MIMXRT798 SoC and MIMXRT700-EVK board, see these references:

• i.MX RT700 Website

Supported Features

NXP considers the MIMXRT700-EVK as a superset board for the i.MX RT7xx family of MCUs. This board is a focus for NXP’s Full Platform Support for Zephyr, to better enable the entire RT7xx family. NXP prioritizes enabling this board with new support for Zephyr features.

The mimxrt700_evk board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

mimxrt700_evk

/

mimxrt798s/cm33_cpu0mimxrt798s/cm33_cpu1

mimxrt700_evk@/mimxrt798s/cm33_cpu0 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33F CPU1	arm,cortex-m33f
ADC	on-chip	LPC LPADC1	nxp,lpc-lpadc
Clock control	on-chip	LPC SYSCON & CLKCTL IP node8	nxp,lpc-syscon
	on-chip	Generic fixed-rate clock provider1	fixed-clock
Counter	on-chip	NXP MCUX Standard Timer/Counter1 4	nxp,lpc-ctimer
	on-chip	NXP Multirate Timer1	nxp,mrt
	on-chip	NXP Multirate Timer Channel1 3	nxp,mrt-channel
DMA	on-chip	NXP MCUX EDMA controller1 1	nxp,mcux-edma
GPIO & Headers	on-chip	Kinetis GPIO2 6	nxp,kinetis-gpio
I2C	on-chip	NXP LPI2C controller15	nxp,lpi2c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8m-nvic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
Multi-Function Device	on-chip	Low Power Flexcomm2 12	nxp,lp-flexcomm
Miscellaneous	on-chip	NXP FlexIO controller1	nxp,flexio
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	arm,armv8m-mpu
MTD	on-board	NXP XSPI MX25UM51345G1	nxp,xspi-mx25um51345g
Pin control	on-chip	LPC I/O Pin Configuration (IOCON)3	nxp,lpc-iocon
	on-chip	RT600/RT500 Pin Controller1	nxp,rt-iocon-pinctrl
PWM	on-chip	NXP SCTimer PWM1	nxp,sctimer-pwm
Reset controller	on-chip	NXP RSTCTL Peripheral reset controller4	nxp,rstctl
Serial controller	on-chip	NXP LPUART1 13	nxp,lpuart
SPI	on-chip	NXP LPSPI controller1 15	nxp,lpspi
	on-chip	NXP XSPI controller1	nxp,xspi
SRAM	on-chip	Generic on-chip SRAM4	mmio-sram
Timer	on-chip	ARMv8-M System Tick1	arm,armv8m-systick
	on-chip	NXP OS Timer on i.MX-RT5xx/6xx1	nxp,os-timer
USB	on-chip	NXP EHCI USB device mode1 1	nxp,ehci
	on-chip	NXP USB high speed phy that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis platforms if high speed usb is supported on these platforms1	nxp,usbphy
Watchdog	on-chip	LPC Windowed Watchdog Timer1 1	nxp,lpc-wwdt

mimxrt700_evk@/mimxrt798s/cm33_cpu1 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33F CPU1	arm,cortex-m33f
ADC	on-chip	LPC LPADC1	nxp,lpc-lpadc
Clock control	on-chip	LPC SYSCON & CLKCTL IP node8	nxp,lpc-syscon
Counter	on-chip	NXP MCUX Standard Timer/Counter1 2	nxp,lpc-ctimer
GPIO & Headers	on-chip	Kinetis GPIO1 2	nxp,kinetis-gpio
I2C	on-chip	NXP LPI2C controller5	nxp,lpi2c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	arm,v8m-nvic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
Multi-Function Device	on-chip	Low Power Flexcomm1 3	nxp,lp-flexcomm
MMU / MPU	on-chip	ARMv8-M MPU (Memory Protection Unit)1	arm,armv8m-mpu
Pin control	on-chip	LPC I/O Pin Configuration (IOCON)2	nxp,lpc-iocon
	on-chip	RT600/RT500 Pin Controller1	nxp,rt-iocon-pinctrl
Reset controller	on-chip	NXP RSTCTL Peripheral reset controller4	nxp,rstctl
Serial controller	on-chip	NXP LPUART1 3	nxp,lpuart
SPI	on-chip	NXP LPSPI controller4	nxp,lpspi
SRAM	on-chip	Generic on-chip SRAM3	mmio-sram
Timer	on-chip	ARMv8-M System Tick1	arm,armv8m-systick
	on-chip	NXP OS Timer on i.MX-RT5xx/6xx1	nxp,os-timer

Connections and IOs

The MIMXRT798 SoC has IOCON registers, which can be used to configure the functionality of a pin.

Name	Function	Usage
PIO0_6	I2C	I2C SDA
PIO0_7	I2C	I2C SCL
PIO0_31	UART0	UART RX
PIO1_0	UART0	UART TX
PIO0_18	GPIO	GREEN LED
PIO0_9	GPIO	SW5
PIO8_14	UART19	UART TX
PIO8_15	UART19	UART RX
PIO3_0	SPI	SPI MOSI
PIO3_1	SPI	SPI SCK
PIO3_2	SPI	SPI MISO
PIO3_3	SPI	SPI SSEL

System Clock

The MIMXRT700 EVK is configured to use the Systick as a source for the system clock.

HiFi1 DSP Core

One can build a Zephyr application for the i.MX RT700 HiFi 1 DSP core by targeting the HiFi 1 SOC. Xtensa toolchain supporting RT700 DSP cores is included in Zephyr SDK.

To build the hello_world sample for the i.MX RT700 HiFi 1 DSP core:

# From the root of the zephyr repository
west build -b mimxrt700_evk/mimxrt798s/hifi1 samples/hello_world

HiFi4 DSP Core

One can build a Zephyr application for the i.MX RT700 HiFi 4 DSP core by targeting the HiFi 4 SOC. Xtensa toolchain supporting RT700 DSP cores is included in Zephyr SDK.

To build the hello_world sample for the i.MX RT700 HiFi 4 DSP core:

# From the root of the zephyr repository
west build -b mimxrt700_evk/mimxrt798s/hifi4 samples/hello_world

Programming and Debugging

The mimxrt700_evk board supports the runners and associated west commands listed below.

	flash	debug	attach	debugserver	rtt
jlink	✅ (default)	✅ (default)	✅	✅	✅
linkserver	✅	✅	✅	✅

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.

LinkServerJLink External

1. Install the LinkServer Debug Host Tools and make sure they are in your search path.

2. To put the board in DFU mode to program the firmware, short jumper J20.

3. To update the debug firmware, please follow the instructions on MIMXRT700-EVK Debug Firmware

Configuring a Console

Connect a USB cable from your PC to J54, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:

• Speed: 115200

• Data: 8 bits

• Parity: None

• Stop bits: 1

Flashing

Here is an example for the Hello World application. This example uses the J-Link Debug Host Tools as default.

# From the root of the zephyr repository
west build -b mimxrt700_evk/mimxrt798s/cm33_cpu0 samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:

*** Booting Zephyr OS v3.7.0 ***
Hello World! mimxrt700_evk/mimxrt798s/cm33_cpu0

Debugging

Here is an example for the Hello World application. This example uses the J-Link Debug Host Tools as default.

# From the root of the zephyr repository
west build -b mimxrt700_evk/mimxrt798s/cm33_cpu0 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

*** Booting Zephyr OS v3.7.0 ***
Hello World! mimxrt700_evk/mimxrt798s/cm33_cpu0

Support Resources for Zephyr

• NXP Zephyr Downstream Software Development Kit

• MCUXpresso for VS Code, wiki documentation and Zephyr lab guides

• NXP Zephyr Knowledge Hub

• NXP’s Zephyr landing page (including training resources)

• NXP Support Community forum for Zephyr