i.MX8MP EVK

Board Overview

Name:

imx8mp_evk

Vendor:

NXP Semiconductors

Architecture:

arm, arm64, xtensa

SoC:

mimx8ml8

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Overview

i.MX8M Plus LPDDR4 EVK board is based on NXP i.MX8M Plus applications processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. Zephyr OS is ported to run on the Cortex®-A53 core.

• Board features:

  • RAM: 2GB LPDDR4

  • Storage:

    • SanDisk 16GB eMMC5.1

    • Micron 32MB QSPI NOR

    • microSD Socket

  • Wireless:

    • WiFi: 2.4/5GHz IEEE 802.11b/g/n

    • Bluetooth: v4.1

  • USB:

    • OTG - 2x type C

  • Ethernet

  • PCI-E M.2

  • Connectors:

    • 40-Pin Dual Row Header

  • LEDs:

    • 1x Power status LED

    • 1x UART LED

  • Debug

    • JTAG 20-pin connector

    • MicroUSB for UART debug, two COM ports for A53 and M4

More information about the board can be found at the NXP website.

Supported Features

The imx8mp_evk board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

imx8mp_evk

/

mimx8ml8/a53mimx8ml8/a53/smpmimx8ml8/adspmimx8ml8/m7mimx8ml8/m7/ddr

imx8mp_evk/mimx8ml8/a53 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A53 CPU1 3	arm,cortex-a53
CAN	on-chip	NXP FlexCAN CANFD controller1 1	nxp,flexcan-fd
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
Ethernet	on-chip	NXP ENET1G IP Module1	nxp,enet1g
	on-chip	NXP ENET MAC/L2 Device1	nxp,enet-mac
	on-board	Realtek RTL8211F Ethernet PHY device1	realtek,rtl8211f
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1	nxp,enet-ptp-clock
GPIO & Headers	on-chip	i.MX GPIO2 3	nxp,imx-gpio
	on-board	PCA6416 I2C-based GPIO expander1	nxp,pca6416
I2C	on-chip	NXP II2C1 5	nxp,ii2c
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	arm,gic-v3
MDIO	on-chip	NXP ENET MDIO Features1	nxp,enet-mdio
Miscellaneous	on-chip	NXP i.MX Resource Domain Controller (RDC)1	nxp,rdc
PHY	on-board	Simple GPIO controlled CAN transceiver1 1	can-transceiver-gpio
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 1	nxp,imx-iuart
Timer	on-chip	NXP MCUX General-Purpose Timer (GPT)2	nxp,imx-gpt
	on-chip	per-core ARM architected timer1	arm,armv8-timer

imx8mp_evk/mimx8ml8/a53/smp target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A53 CPU2 2	arm,cortex-a53
CAN	on-chip	NXP FlexCAN CANFD controller2	nxp,flexcan-fd
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
Ethernet	on-chip	NXP ENET1G IP Module1	nxp,enet1g
	on-chip	NXP ENET MAC/L2 Device1	nxp,enet-mac
	on-board	Realtek RTL8211F Ethernet PHY device1	realtek,rtl8211f
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1	nxp,enet-ptp-clock
GPIO & Headers	on-chip	i.MX GPIO5	nxp,imx-gpio
I2C	on-chip	NXP II2C6	nxp,ii2c
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	arm,gic-v3
MDIO	on-chip	NXP ENET MDIO Features1	nxp,enet-mdio
Miscellaneous	on-chip	NXP i.MX Resource Domain Controller (RDC)1	nxp,rdc
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Power management CPU operations	on-board	Power State Coordination Interface (PSCI) version 0.21	arm,psci-0.2
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 1	nxp,imx-iuart
Timer	on-chip	NXP MCUX General-Purpose Timer (GPT)2	nxp,imx-gpt
	on-chip	per-core ARM architected timer1	arm,armv8-timer

imx8mp_evk/mimx8ml8/adsp target

Type	Location	Description	Compatible
CPU	on-chip	Cadence Tensilica Xtensa LX6 CPU1	cdns,tensilica-xtensa-lx6
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
	on-chip	Generic fixed-rate clock provider1	fixed-clock
DAI	on-chip	NXP Synchronous Audio Interface (SAI)1	nxp,dai-sai
	on-chip	NXP PDM MICFIL1	nxp,dai-micfil
DMA	on-chip	NXP SDMA1	nxp,sdma
Interrupt controller	on-chip	i.MX DSP interrupt controller1	nxp,irqsteer-intc
	on-chip	i.MX IRQ_STEER master3	nxp,irqsteer-master
	on-chip	Xtensa Core interrupt controller1	cdns,xtensa-core-intc
IPM	on-chip	i.MX Messaging Unit1	nxp,imx-mu
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1	nxp,imx-iuart
SRAM	on-chip	Generic on-chip SRAM2	mmio-sram

imx8mp_evk/mimx8ml8/m7 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	arm,cortex-m7
ARM architecture	on-chip	i.MX ITCM (Instruction Tightly Coupled Memory)1	nxp,imx-itcm
	on-chip	i.MX DTCM (Data Tightly Coupled Memory)1	nxp,imx-dtcm
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
GPIO & Headers	on-chip	i.MX GPIO1 4	nxp,imx-gpio
I2C	on-chip	NXP II2C6	nxp,ii2c
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	arm,v7m-nvic
IPM	on-chip	i.MX Messaging Unit1	nxp,imx-mu
MMU / MPU	on-chip	ARMv7-M Memory Protection Unit (MPU)1	arm,armv7m-mpu
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 1	nxp,imx-iuart
SPI	on-chip	NXP i.MX ECSPI controller3	nxp,imx-ecspi
Timer	on-chip	ARMv7-M System Tick1	arm,armv7m-systick

imx8mp_evk/mimx8ml8/m7/ddr target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	arm,cortex-m7
ARM architecture	on-chip	i.MX ITCM (Instruction Tightly Coupled Memory)1	nxp,imx-itcm
	on-chip	i.MX DTCM (Data Tightly Coupled Memory)1	nxp,imx-dtcm
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
GPIO & Headers	on-chip	i.MX GPIO1 4	nxp,imx-gpio
I2C	on-chip	NXP II2C6	nxp,ii2c
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	arm,v7m-nvic
IPM	on-chip	i.MX Messaging Unit1	nxp,imx-mu
MMU / MPU	on-chip	ARMv7-M Memory Protection Unit (MPU)1	arm,armv7m-mpu
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 1	nxp,imx-iuart
SPI	on-chip	NXP i.MX ECSPI controller3	nxp,imx-ecspi
Timer	on-chip	ARMv7-M System Tick1	arm,armv7m-systick

Devices

System Clock

This board configuration uses a system clock frequency of 8 MHz.

The M7 Core is configured to run at a 800 MHz clock speed.

Serial Port

This board configuration uses a single serial communication channel with the CPU’s UART4.

Programming and Debugging (A53)

The imx8mp_evk board supports the runners and associated west commands listed below.

	flash	debug	rtt	debugserver	attach
jlink	✅ (default)	✅ (default)	✅	✅	✅

There are multiple methods to program and debug Zephyr on the A53 core:

Option 1. Boot Zephyr by Using JLink Runner

The default runner for the board is JLink, connect the EVK board’s JTAG connector to the host computer using a J-Link debugger, power up the board and stop the board at U-Boot command line.

Then use “west flash” or “west debug” command to load the zephyr.bin image from the host computer and start the Zephyr application on A53 core0.

Flash and Run

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b imx8mp_evk/mimx8ml8/a53 samples/hello_world
west flash

Then the following log could be found on UART4 console:

*** Booting Zephyr OS build v4.1.0-3063-g38519ca2c028 ***
Hello World! imx8mp_evk/mimx8ml8/a53

Debug

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b imx8mp_evk/mimx8ml8/a53 samples/hello_world
west debug

Option 2. Boot Zephyr by Using U-Boot Command

U-Boot “cpu” command is used to load and kick Zephyr to Cortex-A secondary Core, Currently it is supported in : Real-Time Edge U-Boot (use the branch “uboot_vxxxx.xx-y.y.y, xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example “uboot_v2023.04-2.9.0” branch is U-Boot v2023.04 used in Real-Time Edge Software release v2.9.0), and pre-build images and user guide can be found at Real-Time Edge Software.

Step 1: Download Zephyr Image into DDR Memory

Firstly need to download Zephyr binary image into DDR memory, it can use tftp:

tftp 0xc0000000 zephyr.bin

Or copy the Zephyr image zephyr.bin SD card and plug the card into the board, for example if copy to the FAT partition of the SD card, use the following U-Boot command to load the image into DDR memory (assuming the SD card is dev 1, fat partition ID is 1, they could be changed based on actual setup):

fatload mmc 1:1 0xc0000000 zephyr.bin;

Step 2: Boot Zephyr

Then use the following command to boot Zephyr on the core0:

dcache off; icache flush; go 0xc0000000;

Or use “cpu” command to boot from secondary Core, for example Core1:

dcache flush; icache flush; cpu 1 release 0xc0000000

Option 3. Boot Zephyr by Using Remoteproc under Linux

When running Linux on the A55 core, it can use the remoteproc framework to load and boot Zephyr, refer to Real-Time Edge user guide for more details. Pre-build images and user guide can be found at Real-Time Edge Software.

Use this configuration to run basic Zephyr applications and kernel tests, for example, with the Basic Synchronization sample:

# From the root of the zephyr repository
west build -b imx8mp_evk/mimx8ml8/a53 samples/synchronization

This will build an image with the synchronization sample app, boot it and display the following console output:

*** Booting Zephyr OS build v4.1.0-3063-g38519ca2c028 ***
thread_a: Hello World from cpu 0 on mimx8mp_evk!
thread_b: Hello World from cpu 0 on mimx8mp_evk!
thread_a: Hello World from cpu 0 on mimx8mp_evk!
thread_b: Hello World from cpu 0 on mimx8mp_evk!
thread_a: Hello World from cpu 0 on mimx8mp_evk!

CAN bus (FlexCAN) (A53)

The FlexCAN controller is a CAN 2.0B controller that supports both standard and extended frames. The FlexCAN controller has two independent FlexCAN modules, FlexCAN1 and FlexCAN2. By default, FlexCAN1 is enabled in the device tree. To enable FlexCAN2, you need to add the following overlay to the device tree: boards/nxp/imx8mp_evk/dts/flexcan2.overlay.

For example, building the Hello World sample with the CAN shell and CAN statistics enabled, and using the FlexCAN1 controller, you can use the following configuration:

# From the root of the zephyr repository
west build -b imx8mp_evk/mimx8ml8/a53 samples/hello_world -- -DCONFIG_SHELL=y -DCONFIG_CAN=y -DCONFIG_CAN_SHELL=y -DCONFIG_STATS=y -DCONFIG_CAN_STATS=y

Programming and Debugging (M7)

The MIMX8MP EVK board doesn’t have QSPI flash for the M7, and it needs to be started by the A53 core. The A53 core is responsible to load the M7 binary application into the RAM, put the M7 in reset, set the M7 Program Counter and Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at bootloader level or after the Linux system has booted.

The M7 can use up to 3 different RAMs (currently, only two configurations are supported: ITCM and DDR). These are the memory mapping for A53 and M7:

Region	Cortex-A53	Cortex-M7 (System Bus)	Cortex-M7 (Code Bus)	Size
OCRAM	0x00900000-0x0098FFFF	0x20200000-0x2028FFFF	0x00900000-0x0098FFFF	576KB
DTCM	0x00800000-0x0081FFFF	0x20000000-0x2001FFFF		128KB
ITCM	0x007E0000-0x007FFFFF		0x00000000-0x0001FFFF	128KB
OCRAM_S	0x00180000-0x00188FFF	0x20180000-0x20188FFF	0x00180000-0x00188FFF	36KB
DDR	0x80000000-0x803FFFFF	0x80200000-0x803FFFFF	0x80000000-0x801FFFFF	2MB

For more information about memory mapping see the i.MX 8M Applications Processor Reference Manual (section 2.1 to 2.3)

At compilation time you have to choose which RAM will be used. This configuration is done based on board name (imx8mp_evk/mimx8ml8/m7 for ITCM and imx8mp_evk/mimx8ml8/m7/ddr for DDR).

There are two methods to load M7 Core images: U-Boot command and Linux remoteproc.

Load and Run M7 Zephyr Image from U-Boot

Load and run Zephyr on M7 from A53 using u-boot by copying the compiled zephyr.bin to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt.

Load the M7 binary onto the desired memory and start its execution using:

ITCM

fatload mmc 0:1 0x48000000 zephyr.bin
cp.b 0x48000000 0x7e0000 20000
bootaux 0x7e0000

DDR

fatload mmc 0:1 0x80000000 zephyr.bin
dcache flush
bootaux 0x80000000

Load and Run M7 Zephyr Image by using Linux remoteproc

Prepare device tree:

The device tree must inlcude CM7 dts node with compatible string “fsl,imx8mn-cm7”, and also need to reserve M4 DDR memory if using DDR code and sys address, and also need to put “m4_reserved” in the list of memory-region property of the cm7 node.

reserved-memory {
         #address-cells = <2>;
         #size-cells = <2>;
         ranges;

         m7_reserved: m4@80000000 {
               no-map;
               reg = <0 0x80000000 0 0x1000000>;
         };
         ...
}


imx8mp-cm7 {
         compatible = "fsl,imx8mn-cm7";
         rsc-da = <0x55000000>;
         clocks = <&clk IMX8MP_CLK_M7_DIV>,
                  <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT>;
         clock-names = "core", "audio";
         mbox-names = "tx", "rx", "rxdb";
         mboxes = <&mu 0 1
                  &mu 1 1
                  &mu 3 1>;
         memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>, <&m7_reserved>;
         status = "okay";
         fsl,startup-delay-ms = <500>;
};

Extra Zephyr Kernel configure item for DDR Image:

If use remotepoc to boot DDR board (imx8mp_evk/mimx8ml8/m7/ddr), also need to enable “CONFIG_ROMSTART_RELOCATION_ROM” in order to put romstart memory section into ITCM because M7 Core will get the first instruction from zero address of ITCM, but romstart relocation will make the storage size of zephyr.bin too large, so we don’t enable it by default in board defconfig.

diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig
index 17542cb4eec..8c30c5b6fa3 100644
--- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig
+++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig
@@ -12,3 +12,4 @@ CONFIG_CONSOLE=y
CONFIG_XIP=y
CONFIG_CODE_DDR=y
+CONFIG_ROMSTART_RELOCATION_ROM=y

Then use the following steps to boot Zephyr kernel:

1. In U-Boot command line execute prepare script:

u-boot=> run prepare_mcore

2. Boot Linux kernel with specified dtb and then boot Zephyr by using remoteproc:

root@imx8mp-lpddr4-evk:~# echo zephyr.elf > /sys/devices/platform/imx8mp-cm7/remoteproc/remoteproc0/firmware
root@imx8mp-lpddr4-evk:~# echo start  > /sys/devices/platform/imx8mp-cm7/remoteproc/remoteproc0/state
[   39.195651] remoteproc remoteproc0: powering up imx-rproc
[   39.203345] remoteproc remoteproc0: Booting fw image zephyr.elf, size 503992
[   39.203388] remoteproc remoteproc0: No resource table in elf
root@imx8mp-lpddr4-evk:~# [   39.711380] remoteproc remoteproc0: remote processor imx-rproc is now up

root@imx8mp-lpddr4-evk:~#

Debugging

MIMX8MP EVK board can be debugged by connecting an external JLink JTAG debugger to the J24 debug connector and to the PC. Then the application can be debugged using the usual way.

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b imx8mp_evk/mimx8ml8/m7 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

*** Booting Zephyr OS build v2.7.99-1310-g2801bf644a91  ***
Hello World! imx8mp_evk

Support Resources for Zephyr

• NXP Zephyr Downstream Software Development Kit

• MCUXpresso for VS Code, wiki documentation and Zephyr lab guides

• NXP Zephyr Knowledge Hub

• NXP’s Zephyr landing page (including training resources)

• NXP Support Community forum for Zephyr