FRDM-MCXE31B
Overview
The FRDM-MCXE31B board is a design and evaluation platform based on the NXP MCXE31B microcontroller (MCU). NXP MCXE31B MCU based on an Arm Cortex-M7 core, running at speeds of up to 160 MHz with a 2.97 to 5.5V supply.
Hardware
MCXE31B Arm Cortex-M7 microcontroller running up to 160 MHz
4MB dual-bank on chip Flash
320KB SRAM + 192KB TCM
2x I2C
6x SPI
16x UART
On-board MCU-Link debugger with CMSIS-DAP
Arduino Header, mikroBUS
For more information about the MCXE31B SoC and FRDM-MCXE31B board, see:
Supported Features
The frdm_mcxe31b board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
frdm_mcxe31b/mcxe31b target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
ARM Cortex-M7 CPU1 |
|
CAN |
on-chip |
NXP FlexCAN controller6 |
|
Clock control |
on-chip |
Fast internal RC oscillator1 |
|
on-chip |
Fast external crystal oscillator1 |
||
on-chip |
Glitchless clock switching Clock Generation module1 |
||
on-chip |
Phase-locked loop1 |
||
Counter |
on-chip |
NXP Periodic Interrupt Timer (PIT)3 |
|
on-chip |
|||
DMA |
on-chip |
NXP MCUX EDMA controller1 |
|
GPIO & Headers |
on-chip |
||
on-board |
GPIO pins exposed on Arduino Uno (R3) headers1 |
||
I2C |
on-chip |
NXP LPI2C controller2 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
NXP SIUL2 External Interrupts Request controller1 |
|
on-chip |
ARMv7-M NVIC (Nested Vectored Interrupt Controller)1 |
||
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
Miscellaneous |
on-chip |
NXP FlexIO controller1 |
|
MTD |
on-chip |
Flash node1 |
|
Pin control |
on-chip |
NXP SIUL2 Pin Controller for MCXE31X SoCs1 |
|
RTC |
on-chip |
NXP Real Time Clock (RTC)1 |
|
Sensors |
on-chip |
NXP low-power analog comparator (LPCMP)3 |
|
Serial controller |
on-chip |
||
SPI |
on-chip |
NXP LPSPI controller6 |
|
SRAM |
on-chip |
Generic on-chip SRAM2 |
|
Timer |
on-chip |
ARMv7-M System Tick1 |
Connections and IOs
Each GPIO port is divided into two banks: low bank, from pin 0 to 15, and high
bank, from pin 16 to 31. For example, PTA2 is the pin 2 of gpioa_l (low
bank), and PTA20 is the pin 4 of gpioa_h (high bank).
The GPIO controller provides the option to route external input pad interrupts to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC. By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller, unless they are explicity configured to be directed to the WKPU interrupt controller, as outlined in dts/bindings/gpio/nxp,siul2-gpio.yaml.
To find information about which GPIOs are compatible with each interrupt controller, refer to the device reference manual.
Name |
Function |
Usage |
|---|---|---|
PTC16 |
GPIO |
Red LED |
PTB22 |
GPIO |
Green LED |
PTC14 |
GPIO |
Blue LED |
PTE3 |
LPUART5_RX |
UART Console |
PTE14 |
LPUART5_TX |
UART Console |
System Clock
The MCXE31B SoC is configured to use PLL running at 160MHz as a source for the system clock.
Serial Port
The MCXE31B LPUART5 is used for the console.
Programming and Debugging
The frdm_mcxe31b board supports the runners and associated west commands listed below.
| flash | debug | attach | debugserver | rtt | |
|---|---|---|---|---|---|
| jlink | ✅ | ✅ | ✅ | ✅ | ✅ |
| linkserver | ✅ (default) | ✅ (default) | ✅ | ✅ |
Build and flash applications as usual (see Building an Application and Run an Application for more details).
Configuring a Debug Probe
A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
Using LinkServer
Linkserver is the default runner for this board, and supports the factory
default MCU-Link firmware. Follow the instructions in
MCU-Link CMSIS-DAP Onboard Debug Probe to reprogram the default MCU-Link
firmware. This only needs to be done if the default onboard debug circuit
firmware was changed. To put the board in ISP mode to program the firmware,
short jumper JP3.
Using J-Link
There are two options. The onboard debug circuit can be updated with Segger
J-Link firmware by following the instructions in
MCU-Link JLink Onboard Debug Probe.
To be able to program the firmware, you need to put the board in ISP mode
by shorting the jumper JP3.
The second option is to attach a J-Link External Debug Probe to the
10-pin SWD connector (J14) of the board.
For both options use the -r jlink option with west to use the jlink runner.
west flash -r jlink
Configuring a Console
Connect a USB cable from your PC to J13, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:
Speed: 115200
Data: 8 bits
Parity: None
Stop bits: 1
Flashing
Here is an example for the Hello World application.
# From the root of the zephyr repository
west build -b frdm_mcxe31b samples/hello_world
west flash
Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:
*** Booting Zephyr OS build v4.2.0-2092-g17e93a718422 ***
Hello World! frdm_mcxe31b/mcxe31b
Debugging
Here is an example for the Hello World application.
# From the root of the zephyr repository
west build -b frdm_mcxe31b samples/hello_world
west debug
Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:
*** Booting Zephyr OS build v4.2.0-2092-g17e93a718422 ***
Hello World! frdm_mcxe31b/mcxe31b
Troubleshooting
Using Segger SystemView and RTT
Note that when using SEGGER SystemView or RTT with this SOC, the RTT control
block address must be set manually within SystemView or the RTT Viewer. The
address provided to the tool should be the location of the _SEGGER_RTT
symbol, which can be found using a debugger or by examining the zephyr.map
file output by the linker.
The RTT control block address must be provided manually because this SOC supports ECC RAM. If the SEGGER tooling searches the ECC RAM space for the control block a fault will occur, provided that ECC is enabled and the RAM segment being searched has not been initialized to a known value.
Support Resources for Zephyr
MCUXpresso for VS Code, wiki documentation and Zephyr lab guides
NXP’s Zephyr landing page (including training resources)