nxp,mcux-edma

Note

An implementation of a driver matching this compatible is available in drivers/dma/dma_mcux_edma.c.

Description

These nodes are “dma” bus nodes.

NXP MCUX EDMA controller

Properties

Properties not inherited from the base binding file.

Name	Type	Details
`dma-channels`	`int`	Number of DMA channels supported by the controller This property is required.
`dma-requests`	`int`	Number of DMA request signals supported by the controller. This property is required.
`dmamux-reg-offset`	`int`	The offset value for obtaining DMAMUX register index from DMAMUX channel. Default value means DMAMUX channel is identical with DMAMUX register index
`channel-gap`	`array`	On some platforms, there may be a gap in the channels and this array specifies the start and end of a single gap
`nxp,mem2mem`	`boolean`	If the DMA controller supports memory to memory transfer
`nxp,a_on`	`boolean`	If the DMA controller supports always on
`irq-shared-offset`	`int`	Describes an offset between two channels share the same interrupt entry. Default value means each channel has separate interrupt entry.
`no-error-irq`	`boolean`	If the SoCs don't have a separate interrupt id for error IRQ.
`nxp,version`	`int`	eDMA IP revision number. Legal values: `2`, `3`, `4`
`channels-shared-irq-mask`	`array`	Describes channel enabled mask value on every IRQ. The channel number is mapped to the bit value of array element value. If the interrupt is shared on one channel number, the correspongding bit is set to 1. Please note each element of the array must be 32-bit. If there are more than 32 channels, add one or more 32-bit elements in array(elements should be contiguous). The software will determine the mask value of several elements corresponding to the same interrupt according to the number of channels.
`#dma-cells`	`int`	Number of items to expect in a DMAMUX specifier This property is required.
`dma-channel-mask`	`int`	Bitmask of available DMA channels in ascending order that are not reserved by firmware and are available to the kernel. i.e. first channel corresponds to LSB.
`dma-buf-addr-alignment`	`int`	Memory address alignment requirement for DMA buffers used by the controller.
`dma-buf-size-alignment`	`int`	Memory size alignment requirement for DMA buffers used by the controller.
`dma-copy-alignment`	`int`	Minimal chunk of data possible to be copied by the controller.

Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “nxp,mcux-edma” compatible.

Name	Type	Details
`reg`	`array`	Specifies base physical address(s) and size of DMA and respective DMAMUX register(s) that routes DMA sources This property is required. See Important properties for more information.
`interrupts`	`array`	interrupts for device This property is required. See Important properties for more information.
`status`	`string`	indicates the operational status of a device Legal values: `'ok'`, `'okay'`, `'disabled'`, `'reserved'`, `'fail'`, `'fail-sss'` See Important properties for more information.
`compatible`	`string-array`	compatible strings This property is required. See Important properties for more information.
`reg-names`	`string-array`	name of each register space
`interrupts-extended`	`compound`	extended interrupt specifier for device
`interrupt-names`	`string-array`	name of each interrupt
`interrupt-parent`	`phandle`	phandle to interrupt controller node
`label`	`string`	No description provided for this label See Important properties for more information.
`clocks`	`phandle-array`	Clock gate information
`clock-names`	`string-array`	name of each clock
`#address-cells`	`int`	number of address cells in reg property
`#size-cells`	`int`	number of size cells in reg property
`dmas`	`phandle-array`	DMA channels specifiers
`dma-names`	`string-array`	Provided names of DMA channel specifiers
`io-channels`	`phandle-array`	IO channels specifiers
`io-channel-names`	`string-array`	Provided names of IO channel specifiers
`mboxes`	`phandle-array`	mailbox / IPM channels specifiers
`mbox-names`	`string-array`	Provided names of mailbox / IPM channel specifiers
`power-domains`	`phandle-array`	Power domain specifiers
`power-domain-names`	`string-array`	Provided names of power domain specifiers
`#power-domain-cells`	`int`	Number of cells in power-domains property
`zephyr,deferred-init`	`boolean`	Do not initialize device automatically on boot. Device should be manually initialized using device_init().
`wakeup-source`	`boolean`	Property to identify that a device can be used as wake up source. When this property is provided a specific flag is set into the device that tells the system that the device is capable of wake up the system. Wake up capable devices are disabled (interruptions will not wake up the system) by default but they can be enabled at runtime if necessary.
`zephyr,pm-device-runtime-auto`	`boolean`	Automatically configure the device for runtime power management after the init function runs.
`zephyr,disabling-power-states`	`phandles`	List of power states that will disable this device power.

Specifier cell names

dma cells: mux, source