MIMXRT1015-EVK

Board Overview

MIMXRT1015-EVK

Name:

mimxrt1015_evk

Vendor:

NXP Semiconductors

Architecture:

arm

SoC:

mimxrt1015

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Overview

The i.MX RT1015 expands the i.MX RT crossover processor families by providing high-performance feature set in low-cost LQFP packages, further simplifying board design and layout for customers. The i.MX RT1015 runs on the Arm® Cortex®-M7 core at 500 MHz.

Hardware

• MIMXRT1015DAF5A MCU

• Memory

  • 128 Mbit QSPI Flash

• Connectivity

  • Micro USB host and OTG connectors

  • Arduino interface

• Audio

  • Audio Codec

  • 4-pole audio headphone jack

  • External speaker connection

  • Microphone

• Debug

  • JTAG 10-pin connector

  • OpenSDA with DAPLink

For more information about the MIMXRT1015 SoC and MIMXRT1015-EVK board, see these references:

• i.MX RT1015 Website

• i.MX RT1015 Datasheet

• i.MX RT1015 Reference Manual

• MIMXRT1015-EVK Website

• MIMXRT1015-EVK Quick Reference Guide

• MIMXRT1015-EVK Design Files

External Memory

This platform has the following external memories:

Device	Controller	Status
AT25SF128A	FLEXSPI	Enabled via flash configuration block, which sets up FLEXSPI at boot time.

Supported Features

The mimxrt1015_evk board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

mimxrt1015_evk

/

mimxrt1015

mimxrt1015_evk@/mimxrt1015 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	arm,cortex-m7
ADC	on-chip	NXP MCUA 12B1MSPS SAR ADC1 1	nxp,mcux-12b1msps-sar
ARM architecture	on-chip	MCUX XBAR (Crossbar)3	nxp,mcux-xbar
CAN	on-chip	NXP FlexCAN controller2	nxp,flexcan
	on-chip	NXP FlexCAN CANFD controller1	nxp,flexcan-fd
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
	on-chip	Generic fixed factor clock provider3	fixed-factor-clock
	on-chip	i.MX CCM Fractional PLL1	nxp,imx-ccm-fnpll
	on-chip	i.MX ANATOP (Analog Clock Controller Module) IP node1	nxp,imx-anatop
	on-chip	Generic fixed-rate clock provider4	fixed-clock
Counter	on-chip	NXP MCUX Quad Timer (QTMR)4	nxp,imx-qtmr
	on-chip	NXP MCUX Quad Timer Channel16	nxp,imx-tmr
	on-chip	NXP Periodic Interrupt Timer (PIT)1	nxp,pit
	on-chip	Child node for the Periodic Interrupt Timer node, intended for an individual timer channel4	nxp,pit-channel
Cryptographic accelerator	on-chip	NXP Data Co-Processor (DCP) Crypto accelerator1	nxp,mcux-dcp
Debug	on-chip	ARMv7 instrumentation trace macrocell1	arm,armv7m-itm
Display	on-chip	NXP i.MX eLCDIF (Enhanced LCD Interface) controller1	nxp,imx-elcdif
DMA	on-chip	NXP MCUX EDMA controller1	nxp,mcux-edma
	on-chip	NXP PXP 2D DMA engine1	nxp,pxp
GPIO & Headers	on-chip	i.MX GPIO4	nxp,imx-gpio
	on-board	GPIO pins exposed on Arduino Uno (R3) headers1	arduino-header-r3
I2C	on-chip	NXP LPI2C controller1 3	nxp,lpi2c
I2S	on-chip	NXP mcux SAI-I2S controller3	nxp,mcux-i2s
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	arm,v7m-nvic
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
Memory controller	on-chip	NXP FlexRAM on-chip ram controller If the flexram,bank-spec property is specified, then the flexram will be dynamically reconfigured to the configuration specified at runtime1	nxp,flexram
	on-chip	NXP Smart External Memory Controller (SEMC)1	nxp,imx-semc
Miscellaneous	on-chip	NXP FlexIO controller1	nxp,flexio
MMU / MPU	on-chip	ARMv7-M Memory Protection Unit (MPU)1	arm,armv7m-mpu
MTD	on-board	NXP FlexSPI NOR1	nxp,imx-flexspi-nor
	on-board	Fixed partitions of a flash (or other non-volatile storage) memory1	fixed-partitions
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX RT SoC’s devicetree1	nxp,mcux-rt-pinctrl
	on-chip	i.MX IOMUXC1	nxp,imx-gpr
PWM	on-chip	NXP eFLEX PWM module with mcux-pwm submodules4	nxp,flexpwm
	on-chip	NXP MCUX PWM16	nxp,imx-pwm
RNG	on-chip	Kinetis TRNG (True Random Number Generator)1	nxp,kinetis-trng
RTC	on-chip	NXP SNVS LP/HP RTC1	nxp,imx-snvs-rtc
SDHC	on-chip	NXP imx USDHC controller2	nxp,imx-usdhc
Sensors	on-chip	NXP MCUX QDEC4	nxp,mcux-qdec
	on-chip	NXP on-die temperature monitor1	nxp,tempmon
Serial controller	on-chip	NXP LPUART1 7	nxp,lpuart
SPI	on-chip	NXP FlexSPI controller1	nxp,imx-flexspi
	on-chip	NXP LPSPI controller1 1	nxp,lpspi
Timer	on-chip	ARMv7-M System Tick1	arm,armv7m-systick
	on-chip	NXP MCUX General-Purpose HW Timer (GPT)1	nxp,gpt-hw-timer
	on-chip	NXP MCUX General-Purpose Timer (GPT)1	nxp,imx-gpt
USB	on-chip	NXP EHCI USB device mode1 1	nxp,ehci
	on-chip	NXP USB high speed phy that is used on NXP RTxxxx, RTxxx, MCX, LPC and Kinetis platforms if high speed usb is supported on these platforms2	nxp,usbphy
Video	on-chip	NXP MCUX CMOS sensor interface1	nxp,imx-csi
Watchdog	on-chip	imxRT watchdog2	nxp,imx-wdog

Note

For additional features not yet supported, please also refer to the MIMXRT1064-EVK , which is the superset board in NXP’s i.MX RT10xx family. NXP prioritizes enabling the superset board with NXP’s Full Platform Support for Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1015_evk board.

Connections and I/Os

The MIMXRT1015 SoC has five pairs of pinmux/gpio controllers.

Name	Function	Usage
GPIO_AD_B0_05	GPIO	LED
GPIO_EMC_09	GPIO	SW4
GPIO_AD_B0_06	LPUART1_TX	UART Console
GPIO_AD_B0_07	LPUART1_RX	UART Console
GPIO_EMC_32	LPUART4_TX	UART Console
GPIO_EMC_33	LPUART4_RX	UART Console
GPIO_AD_B1_15	LPI2C1_SDA	I2C SDA
GPIO_AD_B1_14	LPI2C1_CLK	I2C SCL
GPIO_AD_B0_10	LPSPI1_SCK	SPI
GPIO_AD_B0_11	LPSPI1_PCS0	SPI
GPIO_AD_B0_12	LPSPI1_SDO	SPI
GPIO_AD_B0_13	LPSPI1_SDI	SPI
GPIO_AD_B0_14	ADC	ADC1 Channel 1
GPIO_AD_B1_13	ADC	ADC1 Channel 13

System Clock

The MIMXRT1015 SoC is configured to use SysTick as the system clock source, running at 500MHz.

When power management is enabled, the 32 KHz low frequency oscillator on the board will be used as a source for the GPT timer to generate a system clock. This clock enables lower power states, at the cost of reduced resolution

Serial Port

The MIMXRT1015 SoC has four UARTs. LPUART1 is configured for the console, and the remaining are not used.

Programming and Debugging

The mimxrt1015_evk board supports the runners and associated west commands listed below.

	flash	debug	attach	debugserver	rtt
jlink	✅	✅	✅	✅	✅
linkserver	✅ (default)	✅ (default)	✅	✅
pyocd	✅	✅	✅	✅	✅

This board supports 3 debug host tools. Please install your preferred host tool, then follow the instructions in Configuring a Debug Probe to configure the board appropriately.

• LinkServer Debug Host Tools (Default, Supported by NXP)

• J-Link Debug Host Tools (Supported by NXP)

• pyOCD Debug Host Tools (Not supported by NXP)

Once the host tool and board are configured, build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

For the RT1015, J47/J48 are the SWD isolation jumpers, J42 is the DFU mode jumper, and J34 is the 10 pin JTAG/SWD header.

A debug probe is used for both flashing and debugging the board. This board has an LPC-LINK2 Onboard Debug Probe. The default firmware present on this probe is the LPC-Link2 DAPLink Onboard Debug Probe.

Based on the host tool installed, please use the following instructions to setup your debug probe:

• J-Link Debug Host Tools: Using J-Link with LPC-Link2 Probe

• LinkServer Debug Host Tools: Using CMSIS-DAP with LPC-Link2 Probe

• pyOCD Debug Host Tools: Using CMSIS-DAP with LPC-Link2 Probe

Using CMSIS-DAP with LPC-Link2 Probe

1. Follow the instructions provided at LPC-LINK2 CMSIS DAP Onboard Debug Probe to reprogram the default debug probe firmware on this board.

2. Ensure the SWD isolation jumpers are populated

Using J-Link with LPC-Link2 Probe

There are two options: the onboard debug circuit can be updated with Segger J-Link firmware, or a J-Link External Debug Probe can be attached to the EVK.

To update the onboard debug circuit, please do the following:

1. Switch the power source for the EVK to a different source than the debug USB, as the J-Link firmware does not power the EVK via the debug USB.

2. Follow the instructions provided at LPC-Link2 J-Link Onboard Debug Probe to reprogram the default debug probe firmware on this board.

3. Ensure the SWD isolation jumpers are populated.

To attach an external J-Link probe, ensure the SWD isolation jumpers are removed, then connect the probe to the external JTAG/SWD header

Configuring a Console

Regardless of your choice in debug probe, we will use the OpenSDA microcontroller as a usb-to-serial adapter for the serial console. Check that jumpers J45 and J46 are on (they are on by default when boards ship from the factory) to connect UART signals to the OpenSDA microcontroller.

Connect a USB cable from your PC to J41.

Use the following settings with your serial terminal of choice (minicom, putty, etc.):

• Speed: 115200

• Data: 8 bits

• Parity: None

• Stop bits: 1

Flashing

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b mimxrt1015_evk samples/hello_world
west flash

Open a serial terminal, reset the board (press the SW9 button), and you should see the following message in the terminal:

***** Booting Zephyr OS v1.14.0-rc1-1297-g312d75f2459e *****
Hello World! mimxrt1015_evk

Support Resources for Zephyr

• NXP Zephyr Downstream Software Development Kit

• MCUXpresso for VS Code, wiki documentation and Zephyr lab guides

• NXP Zephyr Knowledge Hub

• NXP’s Zephyr landing page (including training resources)

• NXP Support Community forum for Zephyr