FRDM-MCXN236

Overview

FRDM-MCXN236 are compact and scalable development boards for rapid prototyping of MCX N23X MCUs. They offer industry standard headers for easy access to the MCUs I/Os, integrated open-standard serial interfaces, external flash memory and an on-board MCU-Link debugger. MCX N Series are high-performance, low-power microcontrollers with intelligent peripherals and accelerators providing multi-tasking capabilities and performance efficiency.

Hardware

  • MCX-N236 Arm Cortex-M33 microcontroller running at 150 MHz

  • 1MB dual-bank on chip Flash

  • 352 KB RAM

  • USB high-speed (Host/Device) with on-chip HS PHY. HS USB Type-C connectors

  • 8x LP Flexcomms each supporting SPI, I2C, UART

  • 2x FlexCAN with FD, 2x I3Cs, 2x SAI

  • On-board MCU-Link debugger with CMSIS-DAP

  • Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS

For more information about the MCX-N236 SoC and FRDM-MCXN236 board, see:

Supported Features

The FRDM-MCXN236 board configuration supports the following hardware features:

Interface

Controller

Driver/Component

NVIC

on-chip

nested vector interrupt controller

SYSTICK

on-chip

systick

PINMUX

on-chip

pinmux

GPIO

on-chip

gpio

UART

on-chip

serial port-polling; serial port-interrupt

SPI

on-chip

spi

I2C

on-chip

i2c

CLOCK

on-chip

clock_control

FLASH

on-chip

soc flash

WATCHDOG

on-chip

watchdog

VREF

on-chip

regulator

ADC

on-chip

adc

LPCMP

on-chip

sensor(comparator)

FLEXCAN

on-chip

CAN

FLEXIO

on-chip

flexio

DISPLAY

on-chip

flexio; MIPI-DBI. Tested with NXP LCD_PAR_S035 TFT LCD Module

LPTMR

on-chip

counter

Targets available

The default configuration file boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig

Other hardware features are not currently supported by the port.

Connections and IOs

The MCX-N236 SoC has 6 gpio controllers and has pinmux registers which can be used to configure the functionality of a pin.

Name

Function

Usage

P0_PIO1_8

UART

UART RX

P1_PIO1_9

UART

UART TX

System Clock

The MCX-N236 SoC is configured to use PLL0 running at 150MHz as a source for the system clock.

Serial Port

The FRDM-MCXN236 SoC has 8 FLEXCOMM interfaces for serial communication. Flexcomm 4 is configured as UART for the console.

Programming and Debugging

Build and flash applications as usual (see Building an Application and Run an Application for more details).

Configuring a Debug Probe

A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.

Using LinkServer

Linkserver is the default runner for this board, and supports the factory default MCU-Link firmware. Follow the instructions in MCU-Link CMSIS-DAP Onboard Debug Probe to reprogram the default MCU-Link firmware. This only needs to be done if the default onboard debug circuit firmware was changed. To put the board in DFU mode to program the firmware, short jumper JP5.

Configuring a Console

Connect a USB cable from your PC to J10, and use the serial terminal of your choice (minicom, putty, etc.) with the following settings:

  • Speed: 115200

  • Data: 8 bits

  • Parity: None

  • Stop bits: 1

Flashing

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxn236 samples/hello_world
west flash

Open a serial terminal, reset the board (press the RESET button), and you should see the following message in the terminal:

*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxn236/mcxn236

Debugging

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b frdm_mcxn236/mcxn236 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxn236/mcxn236

Troubleshooting

Using Segger SystemView and RTT

Note that when using SEGGER SystemView or RTT with this SOC, the RTT control block address must be set manually within SystemView or the RTT Viewer. The address provided to the tool should be the location of the _SEGGER_RTT symbol, which can be found using a debugger or by examining the zephyr.map file output by the linker.

The RTT control block address must be provided manually because this SOC supports ECC RAM. If the SEGGER tooling searches the ECC RAM space for the control block a fault will occur, provided that ECC is enabled and the RAM segment being searched has not been initialized to a known value.