i.MX95 15x15 EVK

Board Overview

Name:

imx95_evk_15x15

Vendor:

NXP Semiconductors

Architecture:

arm64

SoC:

mimx9596

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Overview

The i.MX95 EVK (IMX95LP4XEVK-15) board is a platform designed to show the most commonly used features of the i.MX 95 applications processor. It is an entry-level development board, which helps developers to get familiar with the processor before investing a large amount of resources in more specific designs. The i.MX 95 device on the board comes in a compact 15 x 15 mm package.

Hardware

• i.MX 95 applications processor

  • The processor integrates up to six Arm Cortex-A55 cores, and supports functional safety with built-in Arm Cortex-M33 and -M7 cores

• DRAM memory: 8-Gbit LPDDR4x DRAM

• eMMC: 64 GB Micron eMMC

• USB interface: Two USB ports: Type-A and Type-C

• Audio codec interface

  • One audio codec WM8962B

  • One 3.5 mm 4-pole CTIA standard audio jack

  • One 4-pin connector to connect speaker

• Ethernet interface

  • ENET2 controller

    • Supports 100 Mbit/s or 1000 Mbit/s RGMII Ethernet with one RJ45 connector connected with an external PHY, RTL8211

  • ENET1 controller

    • Supports 100 Mbit/s or 1000 Mbit/s RGMII Ethernet with one RJ45 connector connected with an external PHY, RTL8211

• M.2 interface: One Wi-Fi/Bluetooth Murata Type-2EL module based on NXP AW612 chip supporting 1x1 Wi-Fi 6 and Bluetooth 5.3

• MIPI CSI interface: Connects to one 22-pin or 36-pin miniSAS connector using x4 lane configuration

• MIPI CSIDSI interface: Connects to one 36-pin miniSAS connector using x4 lane configuration

• LVDS interface: two mini-SAS connectors each with x4-lane configuration

• CAN interface: One 4-pin CAN headers for external connection

• SD card interface: one 4-bit SD3.0 microSD card

• I2C interface: I2C1 to I2C6 controllers

• FT4232H I2C interface: PCT2075 temperature sensor and current monitoring devices

• ADC interface: two 4-channel ADC header

• Debug interface

  • One USB-to-UART/MPSSE device, FT4232H

  • One USB 2.0 Type-C connector (J31) for FT4232H provides quad serial ports

Supported Features

The imx95_evk_15x15 board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

imx95_evk_15x15/mimx9596/a55 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A55 CPU1 5	arm,cortex-a55
Counter	on-chip	NXP Timer/PWM Module (TPM) used as timer6	nxp,tpm-timer
Ethernet	on-chip	NXP i.MX NETC Block Controller1	nxp,imx-netc-blk-ctrl
	on-chip	NXP i.MX NETC Controller1	nxp,imx-netc
	on-chip	NXP i.MX NETC Physical Station Interface (PSI)3	nxp,imx-netc-psi
	on-chip	NXP NETC PTP (Precision Time Protocol) Clock1	nxp,netc-ptp-clock
Firmware	on-chip	System Control and Management Interface (SCMI) shared memory (SHMEM)1	arm,scmi-shmem
	on-chip	System Control and Management Interface (SCMI) with doorbell and shared memory (SHMEM) transport1	arm,scmi
	on-chip	System Control and Management Interface (SCMI) power domain protocol1	arm,scmi-power
	on-chip	System Control and Management Interface (SCMI) clock protocol1	arm,scmi-clock
	on-chip	System Control and Management Interface (SCMI) pinctrl protocol1	arm,scmi-pinctrl
GPIO & Headers	on-chip	i.MX RGPIO5	nxp,imx-rgpio
I2C	on-chip	NXP LPI2C controller8	nxp,lpi2c
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	arm,gic-v3
	on-chip	GIC v3 Interrupt Translation Service1	arm,gic-v3-its
Mailbox	on-chip	NXP i.MX Message Unit as Zephyr MBOX1 5	nxp,mbox-imx-mu
MDIO	on-chip	NXP i.MX NETC External MDIO controller1	nxp,imx-netc-emdio
Pin control	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx93-pinctrl
Serial controller	on-chip	NXP LPUART1 7	nxp,lpuart
Timer	on-chip	per-core ARM architected timer1	arm,armv8-timer

System Clock

This board configuration uses a system clock frequency of 24 MHz for Cortex-A55. Cortex-A55 Core runs up to 1.8 GHz.

Serial Port

This board configuration uses a single serial communication channel with the CPU’s UART1 for Cortex-A55.

Programming and Debugging (A55)

Use this configuration to run basic Zephyr applications and kernel tests, for example, with the Basic Synchronization sample:

1. Build and run the Non-SMP application

# From the root of the zephyr repository
west build -b imx95_evk_15x15/mimx9596/a55 samples/synchronization

This will build an image (zephyr.bin) with the synchronization sample app.

Copy the compiled zephyr.bin to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt.

Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1:

fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000

Or use the following command to kick zephyr.bin to Cortex-A55 Core0:

fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000

It will display the following console output:

*** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 ***
thread_a: Hello World from cpu 0 on imx95_evk_15x15!
thread_b: Hello World from cpu 0 on imx95_evk_15x15!
thread_a: Hello World from cpu 0 on imx95_evk_15x15!
thread_b: Hello World from cpu 0 on imx95_evk_15x15!
thread_a: Hello World from cpu 0 on imx95_evk_15x15!

References

More information can refer to NXP official website: NXP website.