nxp,mipi-dbi-dcnano-lcdif

Vendor: NXP Semiconductors

Note

An implementation of a driver matching this compatible is available in drivers/mipi_dbi/mipi_dbi_nxp_dcnano_lcdif.c.

Description

DBI settings for NXP DCnano LCD controller. DCNano is used in DPI mode by default,
when used in DBI mode the compatible need to change in example overlay. For example:

&lcdif {
    compatible = "nxp,mipi-dbi-dcnano-lcdif";
    clock-frequency = <279000000>;
    wr-period = <14>;
    wr-assert = <6>;
    wr-deassert = <13>;
    cs-assert = <1>;
    cs-deassert = <4>;
};

Properties

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
clock-frequency	int	The DBI clock source frequency. This property is required.
reset-gpios	phandle-array	Reset GPIO pin.
divider	int	Divider of the DBI clock source frequency, the final DBI frequency is clock-frequency / divider.
wr-period	int	How many clock cycles does one write cycle take. This property is required.
wr-assert	int	At which clock cycle to assert E signal for TypeA_ClockedE, or WRX signal for TypeB. This property is required.
wr-deassert	int	At which clock cycle to deassert E signal for TypeA_ClockedE, or WRX signal for TypeB. This property is required.
cs-assert	int	At which clock cycle to assert CSX signal for TypeA_FixedE or TypeB. This property is required.
cs-deassert	int	At which clock cycle to deassert CSX signal for TypeA_FixedE or TypeB. This property is required.
endian	string	Input data endian mode. Legal values: 'no-swap', 'half-word', 'word'
swizzle	string	Bus data output order. Legal values: 'RGB', 'BGR'