Zephyr API Documentation 4.2.99
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stm32_clock_control.h
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1/*
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
3 * Copyright (c) 2016 BayLibre, SAS
4 * Copyright (c) 2017-2022 Linaro Limited.
5 * Copyright (c) 2017 RnDity Sp. z o.o.
6 * Copyright (c) 2023 STMicroelectronics
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
11#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
12
13#include <zephyr/drivers/clock_control.h>
14
15/* Retrieve the main system clock from DTS. */
16#define STM32_HCLK_FREQUENCY DT_PROP(DT_NODELABEL(rcc), clock_frequency)
17
18#if defined(CONFIG_SOC_SERIES_STM32C0X)
19#include <zephyr/dt-bindings/clock/stm32c0_clock.h>
20#elif defined(CONFIG_SOC_SERIES_STM32F0X)
21#include <zephyr/dt-bindings/clock/stm32f0_clock.h>
22#elif defined(CONFIG_SOC_SERIES_STM32F1X)
23#if defined(CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE)
24#include <zephyr/dt-bindings/clock/stm32f10x_clock.h>
25#else
26#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
27#endif
28#elif defined(CONFIG_SOC_SERIES_STM32F3X)
29#include <zephyr/dt-bindings/clock/stm32f3_clock.h>
30#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
31 defined(CONFIG_SOC_SERIES_STM32F4X)
32#include <zephyr/dt-bindings/clock/stm32f4_clock.h>
33#include <zephyr/dt-bindings/clock/stm32f410_clock.h>
34#elif defined(CONFIG_SOC_SERIES_STM32F7X)
35#include <zephyr/dt-bindings/clock/stm32f7_clock.h>
36#elif defined(CONFIG_SOC_SERIES_STM32G0X)
37#include <zephyr/dt-bindings/clock/stm32g0_clock.h>
38#elif defined(CONFIG_SOC_SERIES_STM32G4X)
39#include <zephyr/dt-bindings/clock/stm32g4_clock.h>
40#elif defined(CONFIG_SOC_SERIES_STM32L0X)
41#include <zephyr/dt-bindings/clock/stm32l0_clock.h>
42#elif defined(CONFIG_SOC_SERIES_STM32L1X)
43#include <zephyr/dt-bindings/clock/stm32l1_clock.h>
44#elif defined(CONFIG_SOC_SERIES_STM32L4X)
45#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
46#elif defined(CONFIG_SOC_SERIES_STM32L5X)
47#include <zephyr/dt-bindings/clock/stm32l5_clock.h>
48#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
49#include <zephyr/dt-bindings/clock/stm32mp2_clock.h>
50#elif defined(CONFIG_SOC_SERIES_STM32WBX)
51#include <zephyr/dt-bindings/clock/stm32wb_clock.h>
52#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
53#include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
54#elif defined(CONFIG_SOC_SERIES_STM32WLX)
55#include <zephyr/dt-bindings/clock/stm32wl_clock.h>
56#elif defined(CONFIG_SOC_SERIES_STM32H5X)
57#include <zephyr/dt-bindings/clock/stm32h5_clock.h>
58#elif defined(CONFIG_SOC_SERIES_STM32H7X)
59#include <zephyr/dt-bindings/clock/stm32h7_clock.h>
60#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
61#include <zephyr/dt-bindings/clock/stm32h7rs_clock.h>
62#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
63#include <zephyr/dt-bindings/clock/stm32mp13_clock.h>
64#elif defined(CONFIG_SOC_SERIES_STM32N6X)
65#include <zephyr/dt-bindings/clock/stm32n6_clock.h>
66#elif defined(CONFIG_SOC_SERIES_STM32U0X)
67#include <zephyr/dt-bindings/clock/stm32u0_clock.h>
68#elif defined(CONFIG_SOC_SERIES_STM32U3X)
69#include <zephyr/dt-bindings/clock/stm32u3_clock.h>
70#elif defined(CONFIG_SOC_SERIES_STM32U5X)
71#include <zephyr/dt-bindings/clock/stm32u5_clock.h>
72#elif defined(CONFIG_SOC_SERIES_STM32WBAX)
73#include <zephyr/dt-bindings/clock/stm32wba_clock.h>
74#else
75#include <zephyr/dt-bindings/clock/stm32_clock.h>
76#endif
77
79#define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
80
82
83#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
84#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
85#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
86#define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
87#define STM32_APB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb4_prescaler)
88#define STM32_APB5_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb5_prescaler)
89#define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler)
90#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
91#define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
92#define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1)
93#define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
94#define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
95
96#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler)
97#define STM32_CORE_PRESCALER STM32_AHB_PRESCALER
98#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
99#define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER
100#endif
101
102#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
103#define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER
104#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
105#define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER
106#else
107#define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER
108#endif
109
110#define STM32_ADC_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc_prescaler)
111#define STM32_ADC12_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc12_prescaler)
112#define STM32_ADC34_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc34_prescaler)
113
114#define STM32_TIMER_PRESCALER DT_PROP(DT_NODELABEL(rcc), timpre)
115
117#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
118#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), dcpre)
119#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
120#define STM32_PPRE1 DT_PROP(DT_NODELABEL(rcc), ppre1)
121#define STM32_PPRE2 DT_PROP(DT_NODELABEL(rcc), ppre2)
122#define STM32_PPRE4 DT_PROP(DT_NODELABEL(rcc), ppre4)
123#define STM32_PPRE5 DT_PROP(DT_NODELABEL(rcc), ppre5)
124#else
125#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre)
126#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
127#define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1)
128#define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2)
129#define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre)
130#define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre)
131#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
132
134#define STM32_AHB5_DIV DT_PROP(DT_NODELABEL(rcc), ahb5_div)
135
136#define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
137
138/* To enable use of IS_ENABLED utility macro, these symbols
139 * should not be defined directly using DT_SAME_NODE.
140 */
141#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
142#define STM32_SYSCLK_SRC_PLL 1
143#endif
144#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
145#define STM32_SYSCLK_SRC_HSI 1
146#endif
147#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
148#define STM32_SYSCLK_SRC_HSE 1
149#endif
150#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
151#define STM32_SYSCLK_SRC_MSI 1
152#endif
153#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
154#define STM32_SYSCLK_SRC_MSIS 1
155#endif
156#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
157#define STM32_SYSCLK_SRC_CSI 1
158#endif
159#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(ic2))
160#define STM32_SYSCLK_SRC_IC2 1
161#endif
162
163#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32n6_rcc, okay)
164#if (DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(cpusw), 0), DT_NODELABEL(rcc)))
165#if (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSI)
166#define STM32_CPUCLK_SRC_HSI 1
167#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_MSI)
168#define STM32_CPUCLK_SRC_MSI 1
169#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSE)
170#define STM32_CPUCLK_SRC_HSE 1
171#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_IC1)
172#define STM32_CPUCLK_SRC_IC1 1
173#endif
174#endif /* cpusw clk source is rcc */
175
176#define STM32_TIMG_PRESCALER DT_PROP(DT_NODELABEL(rcc), timg_prescaler)
177#endif /* rcc node compatible st_stm32n6_rcc and okay */
178
180#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk48), st_stm32_clock_mux, okay)
181#define STM32_CK48_ENABLED 1
182#endif
183
185
186#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
187 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
188 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
189 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
190 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
191 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
192 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \
193 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
194 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
195 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
196 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
197 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay) || \
198 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32mp13_pll_clock, okay)
199#define STM32_PLL_ENABLED 1
200#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
201#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
202#define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p)
203#define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1)
204#define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q)
205#define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1)
206#define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r)
207#define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1)
208#define STM32_PLL_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_s)
209#define STM32_PLL_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_s, 1)
210#define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn)
211#define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1)
212#endif
213
214#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay)
215#define STM32_PLLI2S_ENABLED 1
216#define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR
217#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
218#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
219#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
220#endif
221
222#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f411_plli2s_clock, okay)
223#define STM32_PLLI2S_ENABLED 1
224#define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m)
225#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
226#define STM32_PLLI2S_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_q)
227#define STM32_PLLI2S_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_q, 1)
228#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
229#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
230#endif
231
232#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay)
233#define STM32_PLLSAI_ENABLED 1
234#define STM32_PLLSAI_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai), div_m)
235#define STM32_PLLSAI_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai), mul_n)
236#define STM32_PLLSAI_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_p)
237#define STM32_PLLSAI_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_p, 1)
238#define STM32_PLLSAI_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_q)
239#define STM32_PLLSAI_DIVQ_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divq)
240#if (STM32_PLLSAI_Q_ENABLED && !STM32_PLLSAI_DIVQ_ENABLED) || \
241 (!STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED)
242#error "On STM32F4/STM32F7, both div_q and div_divq must be present if one of them is present"
243#endif
244#define STM32_PLLSAI_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_q, 1)
245#define STM32_PLLSAI_DIVQ_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_divq, 1)
246#define STM32_PLLSAI_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_r)
247#define STM32_PLLSAI_DIVR_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divr)
248#if (STM32_PLLSAI_R_ENABLED && !STM32_PLLSAI_DIVR_ENABLED) || \
249 (!STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED)
250#error "On STM32F4/STM32F7, both div_r and div_divr must be present if one of them is present"
251#endif
252#define STM32_PLLSAI_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_r, 1)
253#define STM32_PLLSAI_DIVR_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_divr, 1)
254#endif
255
256#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay)
257#define STM32_PLLSAI1_ENABLED 1
258#define STM32_PLLSAI1_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai1), div_m)
259#define STM32_PLLSAI1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai1), mul_n)
260#define STM32_PLLSAI1_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_p)
261#define STM32_PLLSAI1_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_p, 1)
262#define STM32_PLLSAI1_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_q)
263#define STM32_PLLSAI1_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_q, 1)
264#define STM32_PLLSAI1_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_r)
265#define STM32_PLLSAI1_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_r, 1)
266#endif
267
268#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay)
269#define STM32_PLLSAI2_ENABLED 1
270#define STM32_PLLSAI2_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai2), div_m)
271#define STM32_PLLSAI2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai2), mul_n)
272#define STM32_PLLSAI2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_p)
273#define STM32_PLLSAI2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_p, 1)
274#define STM32_PLLSAI2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_q)
275#define STM32_PLLSAI2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_q, 1)
276#define STM32_PLLSAI2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_r)
277#define STM32_PLLSAI2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_r, 1)
278#define STM32_PLLSAI2_DIVR_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_divr)
279#define STM32_PLLSAI2_DIVR_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_divr, 1)
280#endif
281
282#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \
283 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \
284 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay) || \
285 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32mp13_pll_clock, okay)
286#define STM32_PLL2_ENABLED 1
287#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
288#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
289#define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p)
290#define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1)
291#define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q)
292#define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1)
293#define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r)
294#define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1)
295#define STM32_PLL2_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_s)
296#define STM32_PLL2_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_s, 1)
297#define STM32_PLL2_T_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_t)
298#define STM32_PLL2_T_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_t, 1)
299#define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn)
300#define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1)
301#endif
302
303#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
304 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \
305 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay) || \
306 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32mp13_pll_clock, okay)
307#define STM32_PLL3_ENABLED 1
308#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
309#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
310#define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
311#define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1)
312#define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
313#define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1)
314#define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
315#define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1)
316#define STM32_PLL3_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_s)
317#define STM32_PLL3_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_s, 1)
318#define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn)
319#define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
320#endif
321
322#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32mp13_pll_clock, okay)
323#define STM32_PLL4_ENABLED 1
324#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
325#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
326#define STM32_PLL4_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_p)
327#define STM32_PLL4_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_p, 1)
328#define STM32_PLL4_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_q)
329#define STM32_PLL4_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_q, 1)
330#define STM32_PLL4_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_r)
331#define STM32_PLL4_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_r, 1)
332#define STM32_PLL4_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), fracn)
333#define STM32_PLL4_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll4), fracn, 1)
334#endif
335
336#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
337#define STM32_PLL_ENABLED 1
338#define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre)
339#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
340#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), usbpre)
341#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
342 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \
343 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay)
344#define STM32_PLL_ENABLED 1
345#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
346#define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv)
347#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), otgfspre)
348#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay)
349#define STM32_PLL_ENABLED 1
350#define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div)
351#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
352#endif
353
354#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32f105_pll2_clock, okay)
355#define STM32_PLL2_ENABLED 1
356#define STM32_PLL2_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul)
357#define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv)
358#endif
359
360#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll1), st_stm32n6_pll_clock, okay)
361#define STM32_PLL1_ENABLED 1
362#define STM32_PLL1_M_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_m)
363#define STM32_PLL1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll1), mul_n)
364#define STM32_PLL1_P1_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p1)
365#define STM32_PLL1_P2_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p2)
366#endif
367
368#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32n6_pll_clock, okay)
369#define STM32_PLL2_ENABLED 1
370#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
371#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
372#define STM32_PLL2_P1_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p1)
373#define STM32_PLL2_P2_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p2)
374#endif
375
376#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32n6_pll_clock, okay)
377#define STM32_PLL3_ENABLED 1
378#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
379#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
380#define STM32_PLL3_P1_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p1)
381#define STM32_PLL3_P2_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p2)
382#endif
383
384#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32n6_pll_clock, okay)
385#define STM32_PLL4_ENABLED 1
386#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
387#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
388#define STM32_PLL4_P1_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p1)
389#define STM32_PLL4_P2_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p2)
390#endif
391
393#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && \
394 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
395#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
396#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
397#define STM32_PLL_SRC_MSI 1
398#endif
399#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
400#define STM32_PLL_SRC_MSIS 1
401#endif
402#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
403#define STM32_PLL_SRC_HSI 1
404#endif
405#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
406#define STM32_PLL_SRC_CSI 1
407#endif
408#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
409#define STM32_PLL_SRC_HSE 1
410#endif
411#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
412#define STM32_PLL_SRC_PLL2 1
413#endif
414
415#endif
416
418#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll2)) && \
419 DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks)
420#define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2))
421#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
422#define STM32_PLL2_SRC_MSI 1
423#endif
424#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
425#define STM32_PLL2_SRC_MSIS 1
426#endif
427#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
428#define STM32_PLL2_SRC_HSI 1
429#endif
430#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
431#define STM32_PLL2_SRC_HSE 1
432#endif
433
434#endif
435
437#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll3)) && \
438 DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks)
439#define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3))
440#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
441#define STM32_PLL3_SRC_MSI 1
442#endif
443#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
444#define STM32_PLL3_SRC_MSIS 1
445#endif
446#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
447#define STM32_PLL3_SRC_HSI 1
448#endif
449#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
450#define STM32_PLL3_SRC_HSE 1
451#endif
452
453#endif
454
456#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll4), okay) && \
457 DT_NODE_HAS_PROP(DT_NODELABEL(pll4), clocks)
458#define DT_PLL4_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll4))
459#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
460#define STM32_PLL4_SRC_MSI 1
461#endif
462#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
463#define STM32_PLL4_SRC_HSI 1
464#endif
465#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
466#define STM32_PLL4_SRC_HSE 1
467#endif
468
469#endif
470
472#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai), okay) && \
473 DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), clocks)
474#define DT_PLLSAI_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai))
475#if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
476#define STM32_PLLSAI_SRC_HSI 1
477#endif
478#if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
479#define STM32_PLLSAI_SRC_HSE 1
480#endif
481
482#endif
483
485#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai1), okay) && \
486 DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), clocks)
487#define DT_PLLSAI1_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai1))
488#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
489#define STM32_PLLSAI1_SRC_MSI 1
490#endif
491#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
492#define STM32_PLLSAI1_SRC_HSI 1
493#endif
494#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
495#define STM32_PLLSAI1_SRC_HSE 1
496#endif
497
498#endif
499
501#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai2), okay) && \
502 DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), clocks)
503#define DT_PLLSAI2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai2))
504#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
505#define STM32_PLLSAI2_SRC_MSI 1
506#endif
507#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
508#define STM32_PLLSAI2_SRC_HSI 1
509#endif
510#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
511#define STM32_PLLSAI2_SRC_HSE 1
512#endif
513
514#endif
515
516/* On STM32F4 series - PLL and PLLSAI share the same source */
517#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) && \
518 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \
519 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL)
520#error "On STM32F4 series, PLL and PLLSAI must have the same source"
521#endif
522
523/* On STM32F7 series - PLL and PLLSAI share the same source */
524#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) && \
525 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \
526 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL)
527#error "On STM32F7 series, PLL and PLLSAI must have the same source"
528#endif
529
530/* On STM32L4 series - PLL / PLLSAI1 and PLLSAI2 shared same source */
531#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \
532 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \
533 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI1_CLOCKS_CTRL)
534#error "On STM32L4 series, PLL / PLLSAI1 must have the same source"
535#endif
536#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \
537 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay) && \
538 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI2_CLOCKS_CTRL)
539#error "On STM32L4 series, PLL / PLLSAI2 must have the same source"
540#endif
541#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \
542 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay) && \
543 !DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_PLLSAI2_CLOCKS_CTRL)
544#error "On STM32L4 series, PLLSAI1 / PLLSAI2 must have the same source"
545#endif
546
548
549#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
550#define STM32_LSE_ENABLED 1
551#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
552#define STM32_LSE_DRIVING 0
553#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
554#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay)
555#define STM32_LSE_ENABLED 1
556#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
557#define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability)
558#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
559#else
560#define STM32_LSE_ENABLED 0
561#define STM32_LSE_FREQ 0
562#define STM32_LSE_DRIVING 0
563#define STM32_LSE_BYPASS 0
564#endif
565
566#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
567 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
568#define STM32_MSI_ENABLED 1
569#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
570#endif
571
572#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
573#define STM32_MSI_ENABLED 1
574#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
575#endif
576
577#if defined(CONFIG_SOC_SERIES_STM32L4X) && STM32_MSI_PLL_MODE && !STM32_LSE_ENABLED
578#error "On STM32L4 series, MSI PLL mode requires LSE to be enabled"
579#endif
580
581#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) || \
582 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u3_msi_clock, okay)
583#define STM32_MSIS_ENABLED 1
584#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
585#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
586#else
587#define STM32_MSIS_ENABLED 0
588#define STM32_MSIS_RANGE 0
589#define STM32_MSIS_PLL_MODE 0
590#endif
591
592#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay) || \
593 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u3_msi_clock, okay)
594#define STM32_MSIK_ENABLED 1
595#define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range)
596#define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode)
597#else
598#define STM32_MSIK_ENABLED 0
599#define STM32_MSIK_RANGE 0
600#define STM32_MSIK_PLL_MODE 0
601#endif
602
603#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay)
604#define STM32_CSI_ENABLED 1
605#define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
606#else
607#define STM32_CSI_FREQ 0
608#endif
609
610#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay)
611#define STM32_LSI_ENABLED 1
612#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency)
613#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi1), fixed_clock, okay)
614#define STM32_LSI_ENABLED 1
615#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency)
616#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi2), fixed_clock, okay)
617#define STM32_LSI_ENABLED 1
618#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency)
619#else
620#define STM32_LSI_FREQ 0
621#endif
622
623#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay)
624#define STM32_HSI_DIV_ENABLED 0
625#define STM32_HSI_ENABLED 1
626#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
627#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \
628 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32l0_hsi_clock, okay) \
629 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \
630 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) \
631 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32n6_hsi_clock, okay)
632#define STM32_HSI_DIV_ENABLED 1
633#define STM32_HSI_ENABLED 1
634#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
635#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
636#else
637#define STM32_HSI_DIV_ENABLED 0
638#define STM32_HSI_DIVISOR 1
639#define STM32_HSI_FREQ 0
640#endif
641
642#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay)
643#define STM32_HSE_ENABLED 1
644#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
645#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
646#define STM32_HSE_ENABLED 1
647#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
648#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
649#define STM32_HSE_CSS DT_PROP(DT_NODELABEL(clk_hse), css_enabled)
650#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
651#define STM32_HSE_ENABLED 1
652#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
653#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
654#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
655#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wba_hse_clock, okay)
656#define STM32_HSE_ENABLED 1
657#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
658#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
659#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32n6_hse_clock, okay)
660#define STM32_HSE_ENABLED 1
661#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
662#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
663#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
664#else
665#define STM32_HSE_FREQ 0
666#endif
667
668#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), fixed_clock, okay)
669#define STM32_HSI48_ENABLED 1
670#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
671#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), st_stm32_hsi48_clock, okay)
672#define STM32_HSI48_ENABLED 1
673#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
674#define STM32_HSI48_CRS_USB_SOF DT_PROP(DT_NODELABEL(clk_hsi48), crs_usb_sof)
675#endif
676
677#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay)
678#define STM32_CKPER_ENABLED 1
679#endif
680
681#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(cpusw), st_stm32_clock_mux, okay)
682#define STM32_CPUSW_ENABLED 1
683#endif
684
685#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic1), st_stm32n6_ic_clock_mux, okay)
686#define STM32_IC1_ENABLED 1
687#define STM32_IC1_PLL_SRC DT_PROP(DT_NODELABEL(ic1), pll_src)
688#define STM32_IC1_DIV DT_PROP(DT_NODELABEL(ic1), ic_div)
689#endif
690
691#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic2), st_stm32n6_ic_clock_mux, okay)
692#define STM32_IC2_ENABLED 1
693#define STM32_IC2_PLL_SRC DT_PROP(DT_NODELABEL(ic2), pll_src)
694#define STM32_IC2_DIV DT_PROP(DT_NODELABEL(ic2), ic_div)
695#endif
696
697#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic3), st_stm32n6_ic_clock_mux, okay)
698#define STM32_IC3_ENABLED 1
699#define STM32_IC3_PLL_SRC DT_PROP(DT_NODELABEL(ic3), pll_src)
700#define STM32_IC3_DIV DT_PROP(DT_NODELABEL(ic3), ic_div)
701#endif
702
703#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic4), st_stm32n6_ic_clock_mux, okay)
704#define STM32_IC4_ENABLED 1
705#define STM32_IC4_PLL_SRC DT_PROP(DT_NODELABEL(ic4), pll_src)
706#define STM32_IC4_DIV DT_PROP(DT_NODELABEL(ic4), ic_div)
707#endif
708
709#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic5), st_stm32n6_ic_clock_mux, okay)
710#define STM32_IC5_ENABLED 1
711#define STM32_IC5_PLL_SRC DT_PROP(DT_NODELABEL(ic5), pll_src)
712#define STM32_IC5_DIV DT_PROP(DT_NODELABEL(ic5), ic_div)
713#endif
714
715#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic6), st_stm32n6_ic_clock_mux, okay)
716#define STM32_IC6_ENABLED 1
717#define STM32_IC6_PLL_SRC DT_PROP(DT_NODELABEL(ic6), pll_src)
718#define STM32_IC6_DIV DT_PROP(DT_NODELABEL(ic6), ic_div)
719#endif
720
721#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic7), st_stm32n6_ic_clock_mux, okay)
722#define STM32_IC7_ENABLED 1
723#define STM32_IC7_PLL_SRC DT_PROP(DT_NODELABEL(ic7), pll_src)
724#define STM32_IC7_DIV DT_PROP(DT_NODELABEL(ic7), ic_div)
725#endif
726
727#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic8), st_stm32n6_ic_clock_mux, okay)
728#define STM32_IC8_ENABLED 1
729#define STM32_IC8_PLL_SRC DT_PROP(DT_NODELABEL(ic8), pll_src)
730#define STM32_IC8_DIV DT_PROP(DT_NODELABEL(ic8), ic_div)
731#endif
732
733#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic9), st_stm32n6_ic_clock_mux, okay)
734#define STM32_IC9_ENABLED 1
735#define STM32_IC9_PLL_SRC DT_PROP(DT_NODELABEL(ic9), pll_src)
736#define STM32_IC9_DIV DT_PROP(DT_NODELABEL(ic9), ic_div)
737#endif
738
739#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic10), st_stm32n6_ic_clock_mux, okay)
740#define STM32_IC10_ENABLED 1
741#define STM32_IC10_PLL_SRC DT_PROP(DT_NODELABEL(ic10), pll_src)
742#define STM32_IC10_DIV DT_PROP(DT_NODELABEL(ic10), ic_div)
743#endif
744
745#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic11), st_stm32n6_ic_clock_mux, okay)
746#define STM32_IC11_ENABLED 1
747#define STM32_IC11_PLL_SRC DT_PROP(DT_NODELABEL(ic11), pll_src)
748#define STM32_IC11_DIV DT_PROP(DT_NODELABEL(ic11), ic_div)
749#endif
750
751#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic12), st_stm32n6_ic_clock_mux, okay)
752#define STM32_IC12_ENABLED 1
753#define STM32_IC12_PLL_SRC DT_PROP(DT_NODELABEL(ic12), pll_src)
754#define STM32_IC12_DIV DT_PROP(DT_NODELABEL(ic12), ic_div)
755#endif
756
757#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic13), st_stm32n6_ic_clock_mux, okay)
758#define STM32_IC13_ENABLED 1
759#define STM32_IC13_PLL_SRC DT_PROP(DT_NODELABEL(ic13), pll_src)
760#define STM32_IC13_DIV DT_PROP(DT_NODELABEL(ic13), ic_div)
761#endif
762
763#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic14), st_stm32n6_ic_clock_mux, okay)
764#define STM32_IC14_ENABLED 1
765#define STM32_IC14_PLL_SRC DT_PROP(DT_NODELABEL(ic14), pll_src)
766#define STM32_IC14_DIV DT_PROP(DT_NODELABEL(ic14), ic_div)
767#endif
768
769#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic15), st_stm32n6_ic_clock_mux, okay)
770#define STM32_IC15_ENABLED 1
771#define STM32_IC15_PLL_SRC DT_PROP(DT_NODELABEL(ic15), pll_src)
772#define STM32_IC15_DIV DT_PROP(DT_NODELABEL(ic15), ic_div)
773#endif
774
775#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic16), st_stm32n6_ic_clock_mux, okay)
776#define STM32_IC16_ENABLED 1
777#define STM32_IC16_PLL_SRC DT_PROP(DT_NODELABEL(ic16), pll_src)
778#define STM32_IC16_DIV DT_PROP(DT_NODELABEL(ic16), ic_div)
779#endif
780
781#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic17), st_stm32n6_ic_clock_mux, okay)
782#define STM32_IC17_ENABLED 1
783#define STM32_IC17_PLL_SRC DT_PROP(DT_NODELABEL(ic17), pll_src)
784#define STM32_IC17_DIV DT_PROP(DT_NODELABEL(ic17), ic_div)
785#endif
786
787#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic18), st_stm32n6_ic_clock_mux, okay)
788#define STM32_IC18_ENABLED 1
789#define STM32_IC18_PLL_SRC DT_PROP(DT_NODELABEL(ic18), pll_src)
790#define STM32_IC18_DIV DT_PROP(DT_NODELABEL(ic18), ic_div)
791#endif
792
793#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic19), st_stm32n6_ic_clock_mux, okay)
794#define STM32_IC19_ENABLED 1
795#define STM32_IC19_PLL_SRC DT_PROP(DT_NODELABEL(ic19), pll_src)
796#define STM32_IC19_DIV DT_PROP(DT_NODELABEL(ic19), ic_div)
797#endif
798
799#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic20), st_stm32n6_ic_clock_mux, okay)
800#define STM32_IC20_ENABLED 1
801#define STM32_IC20_PLL_SRC DT_PROP(DT_NODELABEL(ic20), pll_src)
802#define STM32_IC20_DIV DT_PROP(DT_NODELABEL(ic20), ic_div)
803#endif
804
806
812
814
815#define STM32_CLOCK_INFO(clk_index, node_id) \
816 { \
817 .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \
818 .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) & \
819 GENMASK(STM32_CLOCK_DIV_SHIFT - 1, 0), \
820 .div = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) >> \
821 STM32_CLOCK_DIV_SHIFT, \
822 }
823#define STM32_DT_CLOCKS(node_id) \
824 { \
825 LISTIFY(DT_NUM_CLOCKS(node_id), \
826 STM32_CLOCK_INFO, (,), node_id) \
827 }
828
829#define STM32_DT_INST_CLOCKS(inst) \
830 STM32_DT_CLOCKS(DT_DRV_INST(inst))
831
832#define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) ||
833#define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \
834 (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0)
835
836#define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) ||
837#define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \
838 (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0)
839
841
847#define STM32_DT_CLKSEL_REG_GET(clock) \
848 (((clock) >> STM32_DT_CLKSEL_REG_SHIFT) & STM32_DT_CLKSEL_REG_MASK)
849
855#define STM32_DT_CLKSEL_SHIFT_GET(clock) \
856 (((clock) >> STM32_DT_CLKSEL_SHIFT_SHIFT) & STM32_DT_CLKSEL_SHIFT_MASK)
857
863#define STM32_DT_CLKSEL_MASK_GET(clock) \
864 (((clock) >> STM32_DT_CLKSEL_MASK_SHIFT) & STM32_DT_CLKSEL_MASK_MASK)
865
871#define STM32_DT_CLKSEL_VAL_GET(clock) \
872 (((clock) >> STM32_DT_CLKSEL_VAL_SHIFT) & STM32_DT_CLKSEL_VAL_MASK)
873
874#if defined(STM32_HSE_CSS)
883void stm32_hse_css_callback(void);
884#endif
885
886#ifdef CONFIG_SOC_SERIES_STM32WB0X
891typedef void (*lsi_update_cb_t)(uint32_t new_lsi_frequency);
892
904int stm32wb0_register_lsi_update_callback(lsi_update_cb_t cb);
905#endif /* CONFIG_SOC_SERIES_STM32WB0X */
906
907#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */
clock_control.h
Main header file for clock control driver API.
uint32_t
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
stm32_clock.h
STM32_CLOCK_DIV_SHIFT
#define STM32_CLOCK_DIV_SHIFT
Definition stm32_clock.h:27
stm32c0_clock.h
stm32f0_clock.h
stm32f10x_clock.h
stm32f1_clock.h
stm32f3_clock.h
stm32f410_clock.h
stm32f4_clock.h
stm32f7_clock.h
stm32g0_clock.h
stm32g4_clock.h
stm32h5_clock.h
stm32h7_clock.h
stm32h7rs_clock.h
stm32l0_clock.h
stm32l1_clock.h
stm32l4_clock.h
stm32l5_clock.h
stm32mp13_clock.h
stm32mp2_clock.h
stm32n6_clock.h
stm32u0_clock.h
stm32u3_clock.h
stm32u5_clock.h
stm32wb0_clock.h
stm32wb_clock.h
stm32wba_clock.h
stm32wl_clock.h
stm32_pclken
Driver structure definition.
Definition stm32_clock_control.h:807
stm32_pclken::div
uint32_t div
Definition stm32_clock_control.h:809
stm32_pclken::bus
uint32_t bus
Definition stm32_clock_control.h:808
stm32_pclken::enr
uint32_t enr
Definition stm32_clock_control.h:810