stm32f410_clock.h File Reference

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Macros
#define	DCKCFGR_REG   0x8C
	RCC_DCKCFGR register offset.
#define	DCKCFGR2_REG   0x94
#define	CKDFSDM2A_SEL(val)
	Device domain clocks selection helpers.
#define	CKDFSDM1A_SEL(val)
#define	SAI1A_SEL(val)
#define	SAI1B_SEL(val)
#define	I2S1_SEL(val)
#define	I2S2_SEL(val)
#define	CKDFSDM_SEL(val)
#define	I2CFMP1_SEL(val)
	DCKCFGR2 devices.
#define	CK48M_SEL(val)
#define	SDIO_SEL(val)
#define	LPTIM1_SEL(val)

Macro Definition Documentation

CK48M_SEL

#define CK48M_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)

CKDFSDM1A_SEL

#define CKDFSDM1A_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG)

CKDFSDM2A_SEL

#define CKDFSDM2A_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG)

Device domain clocks selection helpers.

DCKCFGR devices

CKDFSDM_SEL

#define CKDFSDM_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 1, 31, DCKCFGR_REG)

DCKCFGR2_REG

#define DCKCFGR2_REG   0x94

DCKCFGR_REG

#define DCKCFGR_REG   0x8C

RCC_DCKCFGR register offset.

I2CFMP1_SEL

#define I2CFMP1_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)

DCKCFGR2 devices.

I2S1_SEL

#define I2S1_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 25, DCKCFGR_REG)

I2S2_SEL

#define I2S2_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 27, DCKCFGR_REG)

LPTIM1_SEL

#define LPTIM1_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 30, DCKCFGR2_REG)

SAI1A_SEL

#define SAI1A_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG)

SAI1B_SEL

#define SAI1B_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG)

SDIO_SEL

#define SDIO_SEL

(

val

)

Value:

STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)