stm32_common_clocks.h File Reference

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Macros
#define	STM32_SRC_SYSCLK   0x001
	System clock.
#define	STM32_SRC_LSE   0x002
	Fixed clocks
#define	STM32_SRC_LSI   0x003
#define	NO_SEL   0xFF
	Dummy: Add a specifier when no selection is possible.
#define	STM32_MCO_CFGR_REG_MASK   0xFFFFU
	STM32 MCO configuration values.
#define	STM32_MCO_CFGR_REG_SHIFT   0U
#define	STM32_MCO_CFGR_SHIFT_MASK   0x3FU
#define	STM32_MCO_CFGR_SHIFT_SHIFT   16U
#define	STM32_MCO_CFGR_MASK_MASK   0x1FU
#define	STM32_MCO_CFGR_MASK_SHIFT   22U
#define	STM32_MCO_CFGR_VAL_MASK   0x1FU
#define	STM32_MCO_CFGR_VAL_SHIFT   27U
#define	STM32_MCO_CFGR(val, mask, shift, reg)
	STM32 MCO configuration register bit field.
#define	STM32_CLOCK(bus, bit)
	Pack RCC clock register offset and bit in two 32-bit values as expected for the Device Tree clocks property on STM32.

Macro Definition Documentation

NO_SEL

#define NO_SEL   0xFF

Dummy: Add a specifier when no selection is possible.

STM32_CLOCK

#define STM32_CLOCK	(		bus,
			bit )

Value:

(STM32_CLOCK_BUS_##bus) (1 << bit)

Pack RCC clock register offset and bit in two 32-bit values as expected for the Device Tree clocks property on STM32.

Parameters

bus	STM32 bus name (expands to STM32_CLOCK_BUS_{bus})
bit	Clock bit

STM32_MCO_CFGR

#define STM32_MCO_CFGR	(		val,
			mask,
			shift,
			reg )

Value:

        ((((reg) & STM32_MCO_CFGR_REG_MASK) << STM32_MCO_CFGR_REG_SHIFT) |        \
         (((shift) & STM32_MCO_CFGR_SHIFT_MASK) << STM32_MCO_CFGR_SHIFT_SHIFT) |    \
         (((mask) & STM32_MCO_CFGR_MASK_MASK) << STM32_MCO_CFGR_MASK_SHIFT) |        \
         (((val) & STM32_MCO_CFGR_VAL_MASK) << STM32_MCO_CFGR_VAL_SHIFT))

STM32 MCO configuration register bit field.

Parameters

reg	Offset to RCC register holding MCO configuration
shift	Position of field within RCC register (= field LSB's index)
mask	Mask of register field in RCC register
val	Clock configuration field value (0~0x1F)

Note

'reg' range: 0x0~0xFFFF [ 00 : 15 ]

'shift' range: 0~63 [ 16 : 21 ]

'mask' range: 0x00~0x1F [ 22 : 26 ]

'val' range: 0x00~0x1F [ 27 : 31 ]

STM32_MCO_CFGR_MASK_MASK

#define STM32_MCO_CFGR_MASK_MASK   0x1FU

STM32_MCO_CFGR_MASK_SHIFT

#define STM32_MCO_CFGR_MASK_SHIFT   22U

STM32_MCO_CFGR_REG_MASK

#define STM32_MCO_CFGR_REG_MASK   0xFFFFU

STM32 MCO configuration values.

STM32_MCO_CFGR_REG_SHIFT

#define STM32_MCO_CFGR_REG_SHIFT   0U

STM32_MCO_CFGR_SHIFT_MASK

#define STM32_MCO_CFGR_SHIFT_MASK   0x3FU

STM32_MCO_CFGR_SHIFT_SHIFT

#define STM32_MCO_CFGR_SHIFT_SHIFT   16U

STM32_MCO_CFGR_VAL_MASK

#define STM32_MCO_CFGR_VAL_MASK   0x1FU

STM32_MCO_CFGR_VAL_SHIFT

#define STM32_MCO_CFGR_VAL_SHIFT   27U

STM32_SRC_LSE

#define STM32_SRC_LSE   0x002

Fixed clocks

STM32_SRC_LSI

#define STM32_SRC_LSI   0x003

STM32_SRC_SYSCLK

#define STM32_SRC_SYSCLK   0x001

System clock.