Zephyr API Documentation 4.0.0-rc2
A Scalable Open Source RTOS
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stm32f4_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_
8
10
14#define STM32_CLOCK_BUS_AHB1 0x030
15#define STM32_CLOCK_BUS_AHB2 0x034
16#define STM32_CLOCK_BUS_AHB3 0x038
17#define STM32_CLOCK_BUS_APB1 0x040
18#define STM32_CLOCK_BUS_APB2 0x044
19#define STM32_CLOCK_BUS_APB3 0x0A8
20
21#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
22#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
23
25/* RM0386, 0390, 0402, 0430 ยง Dedicated Clock configuration register (RCC_DCKCFGRx) */
26
28/* defined in stm32_common_clocks.h */
30/* Low speed clocks defined in stm32_common_clocks.h */
32#define STM32_SRC_PLL_P (STM32_SRC_LSI + 1)
33#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
34#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
36#define STM32_SRC_PLLI2S_R (STM32_SRC_PLL_R + 1)
37/* I2S_CKIN not supported yet */
38/* #define STM32_SRC_I2S_CKIN TBD */
39
40
41#define STM32_CLOCK_REG_MASK 0xFFU
42#define STM32_CLOCK_REG_SHIFT 0U
43#define STM32_CLOCK_SHIFT_MASK 0x1FU
44#define STM32_CLOCK_SHIFT_SHIFT 8U
45#define STM32_CLOCK_MASK_MASK 0x7U
46#define STM32_CLOCK_MASK_SHIFT 13U
47#define STM32_CLOCK_VAL_MASK 0x7U
48#define STM32_CLOCK_VAL_SHIFT 16U
49
63#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
64 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
65 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
66 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
67 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
68
70#define CFGR_REG 0x08
72#define BDCR_REG 0x70
73
76#define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
77#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG)
78#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
79#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)
80#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)
82#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
83
84#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ */