stm32wba_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_SRC_HSE   (STM32_SRC_LSI + 1)
	Peripheral clock sources.
#define	STM32_SRC_HSI16   (STM32_SRC_HSE + 1)
#define	STM32_SRC_PLL1_P   (STM32_SRC_HSI16 + 1)
	PLL outputs.
#define	STM32_SRC_PLL1_Q   (STM32_SRC_PLL1_P + 1)
#define	STM32_SRC_PLL1_R   (STM32_SRC_PLL1_Q + 1)
#define	STM32_SRC_CLOCK_MIN   STM32_SRC_PLL1_P
#define	STM32_SRC_CLOCK_MAX   STM32_SRC_SYSCLK
#define	STM32_CLOCK_BUS_AHB1   0x088
	Bus clocks (Register address offsets)
#define	STM32_CLOCK_BUS_AHB2   0x08C
#define	STM32_CLOCK_BUS_AHB4   0x094
#define	STM32_CLOCK_BUS_AHB5   0x098
#define	STM32_CLOCK_BUS_APB1   0x09C
#define	STM32_CLOCK_BUS_APB1_2   0x0A0
#define	STM32_CLOCK_BUS_APB2   0x0A4
#define	STM32_CLOCK_BUS_APB7   0x0A8
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB7
#define	STM32_CLOCK_REG_MASK   0xFFU
	STM32WBA clock configuration bit field.
#define	STM32_CLOCK_REG_SHIFT   0U
#define	STM32_CLOCK_SHIFT_MASK   0x1FU
#define	STM32_CLOCK_SHIFT_SHIFT   8U
#define	STM32_CLOCK_MASK_MASK   0x7U
#define	STM32_CLOCK_MASK_SHIFT   13U
#define	STM32_CLOCK_VAL_MASK   0x7U
#define	STM32_CLOCK_VAL_SHIFT   16U
#define	STM32_CLOCK(val, mask, shift, reg)
#define	CCIPR1_REG   0xE0
	RCC_CCIPRx register offset (RM0493.pdf)
#define	CCIPR2_REG   0xE4
#define	CCIPR3_REG   0xE8
#define	BCDR1_REG   0xF0
	RCC_BCDR1 register offset (RM0493.pdf)
#define	USART1_SEL(val)
	Device clk sources selection helpers.
#define	USART2_SEL(val)
#define	I2C1_SEL(val)
#define	LPTIM2_SEL(val)
#define	SPI1_SEL(val)
#define	SYSTICK_SEL(val)
#define	TIMIC_SEL(val)
#define	RNG_SEL(val)
	CCIPR2 devices.
#define	LPUART1_SEL(val)
	CCIPR3 devices.
#define	SPI3_SEL(val)
#define	I2C3_SEL(val)
#define	LPTIM1_SEL(val)
#define	ADC_SEL(val)
#define	RTC_SEL(val)
	BCDR1 devices.

Macro Definition Documentation

ADC_SEL

#define ADC_SEL

(

val

)

Value:

STM32_CLOCK(val, 7, 12, CCIPR3_REG)

BCDR1_REG

#define BCDR1_REG   0xF0

RCC_BCDR1 register offset (RM0493.pdf)

CCIPR1_REG

#define CCIPR1_REG   0xE0

RCC_CCIPRx register offset (RM0493.pdf)

CCIPR2_REG

#define CCIPR2_REG   0xE4

CCIPR3_REG

#define CCIPR3_REG   0xE8

I2C1_SEL

#define I2C1_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 10, CCIPR1_REG)

I2C3_SEL

#define I2C3_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 6, CCIPR3_REG)

LPTIM1_SEL

#define LPTIM1_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 10, CCIPR3_REG)

LPTIM2_SEL

#define LPTIM2_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 18, CCIPR1_REG)

LPUART1_SEL

#define LPUART1_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 0, CCIPR3_REG)

CCIPR3 devices.

RNG_SEL

#define RNG_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 12, CCIPR2_REG)

CCIPR2 devices.

RTC_SEL

#define RTC_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 8, BCDR1_REG)

BCDR1 devices.

SPI1_SEL

#define SPI1_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 20, CCIPR1_REG)

SPI3_SEL

#define SPI3_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 3, CCIPR3_REG)

STM32_CLOCK

#define STM32_CLOCK	(		val,
			mask,
			shift,
			reg )

Value:

        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |    \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x088

Bus clocks (Register address offsets)

STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x08C

STM32_CLOCK_BUS_AHB4

#define STM32_CLOCK_BUS_AHB4   0x094

STM32_CLOCK_BUS_AHB5

#define STM32_CLOCK_BUS_AHB5   0x098

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x09C

STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x0A0

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x0A4

STM32_CLOCK_BUS_APB7

#define STM32_CLOCK_BUS_APB7   0x0A8

STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   0x7U

STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   13U

STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   0xFFU

STM32WBA clock configuration bit field.

• reg (1/2/3) [ 0 : 7 ]
• shift (0..31) [ 8 : 12 ]
• mask (0x1, 0x3, 0x7) [ 13 : 15 ]
• val (0..7) [ 16 : 18 ]

Parameters

reg	RCC_CCIPRx register offset
shift	Position within RCC_CCIPRx.
mask	Mask for the RCC_CCIPRx field.
val	Clock value (0, 1, ... 7).

STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   0U

STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   0x1FU

STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   8U

STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   0x7U

STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   16U

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB7

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_CLOCK_MAX

#define STM32_SRC_CLOCK_MAX   STM32_SRC_SYSCLK

STM32_SRC_CLOCK_MIN

#define STM32_SRC_CLOCK_MIN   STM32_SRC_PLL1_P

STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_LSI + 1)

Peripheral clock sources.

System clock Fixed clocks

STM32_SRC_HSI16

#define STM32_SRC_HSI16   (STM32_SRC_HSE + 1)

STM32_SRC_PLL1_P

#define STM32_SRC_PLL1_P   (STM32_SRC_HSI16 + 1)

PLL outputs.

STM32_SRC_PLL1_Q

#define STM32_SRC_PLL1_Q   (STM32_SRC_PLL1_P + 1)

STM32_SRC_PLL1_R

#define STM32_SRC_PLL1_R   (STM32_SRC_PLL1_Q + 1)

SYSTICK_SEL

#define SYSTICK_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 22, CCIPR1_REG)

TIMIC_SEL

#define TIMIC_SEL

(

val

)

Value:

STM32_CLOCK(val, 1, 31, CCIPR1_REG)

USART1_SEL

#define USART1_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 0, CCIPR1_REG)

Device clk sources selection helpers.

CCIPR1 devices

USART2_SEL

#define USART2_SEL

(

val

)

Value:

STM32_CLOCK(val, 3, 2, CCIPR1_REG)