stm32mp13_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_SRC_HSE   (STM32_SRC_LSI + 1)
	System clock.
#define	STM32_SRC_HSI   (STM32_SRC_HSE + 1)
#define	STM32_SRC_PLL1_P   (STM32_SRC_HSI + 1)
	PLL outputs.
#define	STM32_SRC_PLL2_P   (STM32_SRC_PLL1_P + 1)
#define	STM32_SRC_PLL2_Q   (STM32_SRC_PLL2_P + 1)
#define	STM32_SRC_PLL2_R   (STM32_SRC_PLL2_Q + 1)
#define	STM32_SRC_PLL3_P   (STM32_SRC_PLL2_R + 1)
#define	STM32_SRC_PLL3_Q   (STM32_SRC_PLL3_P + 1)
#define	STM32_SRC_PLL3_R   (STM32_SRC_PLL3_Q + 1)
#define	STM32_SRC_PLL4_P   (STM32_SRC_PLL3_R + 1)
#define	STM32_SRC_PLL4_Q   (STM32_SRC_PLL4_P + 1)
#define	STM32_SRC_PLL4_R   (STM32_SRC_PLL4_Q + 1)
#define	STM32_CLOCK_BUS_APB1   0x700
	Bus clocks.
#define	STM32_CLOCK_BUS_APB2   0x708
#define	STM32_CLOCK_BUS_APB3   0x710
#define	STM32_CLOCK_BUS_APB4   0x728
#define	STM32_CLOCK_BUS_APB4_NS   0x738
#define	STM32_CLOCK_BUS_APB5   0x740
#define	STM32_CLOCK_BUS_APB6   0x748
#define	STM32_CLOCK_BUS_AHB2   0x750
#define	STM32_CLOCK_BUS_AHB4   0x768
#define	STM32_CLOCK_BUS_AHB5   0x778
#define	STM32_CLOCK_BUS_AHB6   0x780
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_APB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_AHB6
#define	MCO1CFGR_REG   0x460
	Device domain clocks selection helpers.
#define	MCO2CFGR_REG   0x464
#define	I2C12CKSELR_REG   0x600
#define	I2C345CKSELR_REG   0x604
#define	SPI2S1CKSELR_REG   0x608
#define	SPI2S23CKSELR_REG   0x60c
#define	SPI45CKSELR_REG   0x610
#define	UART12CKSELR_REG   0x614
#define	UART35CKSELR_REG   0x618
#define	UART4CKSELR_REG   0x61c
#define	UART6CKSELR_REG   0x620
#define	UART78CKSELR_REG   0x624
#define	LPTIM1CKSELR_REG   0x628
#define	LPTIM23CKSELR_REG   0x62c
#define	LPTIM45CKSELR_REG   0x630
#define	SAI1CKSELR_REG   0x634
#define	SAI2CKSELR_REG   0x638
#define	FDCANCKSELR_REG   0x63c
#define	SPDIFCKSELR_REG   0x640
#define	ADC12CKSELR_REG   0x644
#define	SDMMC12CKSELR_REG   0x648
#define	ETH12CKSELR_REG   0x64c
#define	USBCKSELR_REG   0x650
#define	QSPICKSELR_REG   0x654
#define	FMCCKSELR_REG   0x658
#define	RNG1CKSELR_REG   0x65c
#define	STGENCKSELR_REG   0x660
#define	DCMIPPCKSELR_REG   0x664
#define	SAESCKSELR_REG   0x668
#define	MCO1_SEL(val)
	MCO1CFGR / MCO2CFGR devices.
#define	MCO1_PRE(val)
#define	MCO2_SEL(val)
#define	MCO2_PRE(val)
#define	MCOX_ON   BIT(12)
#define	MCO1_SEL_HSI   0
#define	MCO1_SEL_HSE   1
#define	MCO1_SEL_CSI   2
#define	MCO1_SEL_LSI   3
#define	MCO1_SEL_LSE   4
#define	MCO2_SEL_MPU   0
#define	MCO2_SEL_AXI   1
#define	MCO2_SEL_MLAHB   2
#define	MCO2_SEL_PLL4   3
#define	MCO2_SEL_HSE   4
#define	MCO2_SEL_HSI   5
#define	MCO_PRE_DIV_1   0
#define	MCO_PRE_DIV_2   1
#define	MCO_PRE_DIV_3   2
#define	MCO_PRE_DIV_4   3
#define	MCO_PRE_DIV_5   4
#define	MCO_PRE_DIV_6   5
#define	MCO_PRE_DIV_7   6
#define	MCO_PRE_DIV_8   7
#define	MCO_PRE_DIV_9   8
#define	MCO_PRE_DIV_10   9
#define	MCO_PRE_DIV_11   10
#define	MCO_PRE_DIV_12   11
#define	MCO_PRE_DIV_13   12
#define	MCO_PRE_DIV_14   13
#define	MCO_PRE_DIV_15   14
#define	MCO_PRE_DIV_16   15
#define	I2C12_SEL(val)
#define	I2C3_SEL(val)
#define	I2C4_SEL(val)
#define	I2C5_SEL(val)
#define	SPI1_SEL(val)
#define	SPI23_SEL(val)
#define	SPI4_SEL(val)
#define	SPI5_SEL(val)
#define	UART1_SEL(val)
#define	UART2_SEL(val)
#define	UART35_SEL(val)
#define	UART4_SEL(val)
#define	UART6_SEL(val)
#define	UART78_SEL(val)
#define	LPTIME1_SEL(val)
#define	LPTIME2_SEL(val)
#define	LPTIME3_SEL(val)
#define	LPTIME45_SEL(val)
#define	SAI1_SEL(val)
#define	SAI2_SEL(val)
#define	FDCAN_SEL(val)
#define	SPDIF_SEL(val)
#define	ADC1_SEL(val)
#define	ADC2_SEL(val)
#define	SDMMC1_SEL(val)
#define	SDMMC2_SEL(val)
#define	ETH1_SEL(val)
#define	ETH2_SEL(val)
#define	USBPHY_SEL(val)
#define	USBOTG_SEL(val)
#define	QSPI_SEL(val)
#define	FMC_SEL(val)
#define	RNG1_SEL(val)
#define	STGEN_SEL(val)
#define	DCMIPP_SEL(val)
#define	SAES_SEL(val)

Macro Definition Documentation

ADC12CKSELR_REG

#define ADC12CKSELR_REG   0x644

ADC1_SEL

#define ADC1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 0, ADC12CKSELR_REG)

ADC2_SEL

#define ADC2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 2, ADC12CKSELR_REG)

DCMIPP_SEL

#define DCMIPP_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 0, DCMIPPCKSELR_REG)

DCMIPPCKSELR_REG

#define DCMIPPCKSELR_REG   0x664

ETH12CKSELR_REG

#define ETH12CKSELR_REG   0x64c

ETH1_SEL

#define ETH1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 0, ETH12CKSELR_REG)

ETH2_SEL

#define ETH2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 8, ETH12CKSELR_REG)

FDCAN_SEL

#define FDCAN_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 0, FDCANCKSELR_REG)

FDCANCKSELR_REG

#define FDCANCKSELR_REG   0x63c

FMC_SEL

#define FMC_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 0, FMCCKSELR_REG)

FMCCKSELR_REG

#define FMCCKSELR_REG   0x658

I2C12_SEL

#define I2C12_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C12CKSELR_REG)

I2C12CKSELR_REG

#define I2C12CKSELR_REG   0x600

I2C345CKSELR_REG

#define I2C345CKSELR_REG   0x604

I2C3_SEL

#define I2C3_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C345CKSELR_REG)

I2C4_SEL

#define I2C4_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 3, I2C345CKSELR_REG)

I2C5_SEL

#define I2C5_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 6, I2C345CKSELR_REG)

LPTIM1CKSELR_REG

#define LPTIM1CKSELR_REG   0x628

LPTIM23CKSELR_REG

#define LPTIM23CKSELR_REG   0x62c

LPTIM45CKSELR_REG

#define LPTIM45CKSELR_REG   0x630

LPTIME1_SEL

#define LPTIME1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM1CKSELR_REG)

LPTIME2_SEL

#define LPTIME2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM23CKSELR_REG)

LPTIME3_SEL

#define LPTIME3_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 3, LPTIM23CKSELR_REG)

LPTIME45_SEL

#define LPTIME45_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM45CKSELR_REG)

MCO1_PRE

#define MCO1_PRE

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO1CFGR_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO1CFGR_REG)

MCO1CFGR / MCO2CFGR devices.

MCO1_SEL_CSI

#define MCO1_SEL_CSI   2

MCO1_SEL_HSE

#define MCO1_SEL_HSE   1

MCO1_SEL_HSI

#define MCO1_SEL_HSI   0

MCO1_SEL_LSE

#define MCO1_SEL_LSE   4

MCO1_SEL_LSI

#define MCO1_SEL_LSI   3

MCO1CFGR_REG

#define MCO1CFGR_REG   0x460

Device domain clocks selection helpers.

MCO2_PRE

#define MCO2_PRE

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO2CFGR_REG)

MCO2_SEL

#define MCO2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO2CFGR_REG)

MCO2_SEL_AXI

#define MCO2_SEL_AXI   1

MCO2_SEL_HSE

#define MCO2_SEL_HSE   4

MCO2_SEL_HSI

#define MCO2_SEL_HSI   5

MCO2_SEL_MLAHB

#define MCO2_SEL_MLAHB   2

MCO2_SEL_MPU

#define MCO2_SEL_MPU   0

MCO2_SEL_PLL4

#define MCO2_SEL_PLL4   3

MCO2CFGR_REG

#define MCO2CFGR_REG   0x464

MCO_PRE_DIV_1

#define MCO_PRE_DIV_1   0

MCO_PRE_DIV_10

#define MCO_PRE_DIV_10   9

MCO_PRE_DIV_11

#define MCO_PRE_DIV_11   10

MCO_PRE_DIV_12

#define MCO_PRE_DIV_12   11

MCO_PRE_DIV_13

#define MCO_PRE_DIV_13   12

MCO_PRE_DIV_14

#define MCO_PRE_DIV_14   13

MCO_PRE_DIV_15

#define MCO_PRE_DIV_15   14

MCO_PRE_DIV_16

#define MCO_PRE_DIV_16   15

MCO_PRE_DIV_2

#define MCO_PRE_DIV_2   1

MCO_PRE_DIV_3

#define MCO_PRE_DIV_3   2

MCO_PRE_DIV_4

#define MCO_PRE_DIV_4   3

MCO_PRE_DIV_5

#define MCO_PRE_DIV_5   4

MCO_PRE_DIV_6

#define MCO_PRE_DIV_6   5

MCO_PRE_DIV_7

#define MCO_PRE_DIV_7   6

MCO_PRE_DIV_8

#define MCO_PRE_DIV_8   7

MCO_PRE_DIV_9

#define MCO_PRE_DIV_9   8

MCOX_ON

#define MCOX_ON   BIT(12)

QSPI_SEL

#define QSPI_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 0, QSPICKSELR_REG)

QSPICKSELR_REG

#define QSPICKSELR_REG   0x654

RNG1_SEL

#define RNG1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 0, RNG1CKSELR_REG)

RNG1CKSELR_REG

#define RNG1CKSELR_REG   0x65c

SAES_SEL

#define SAES_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 0, SAESCKSELR_REG)

SAESCKSELR_REG

#define SAESCKSELR_REG   0x668

SAI1_SEL

#define SAI1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI1CKSELR_REG)

SAI1CKSELR_REG

#define SAI1CKSELR_REG   0x634

SAI2_SEL

#define SAI2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI2CKSELR_REG)

SAI2CKSELR_REG

#define SAI2CKSELR_REG   0x638

SDMMC12CKSELR_REG

#define SDMMC12CKSELR_REG   0x648

SDMMC1_SEL

#define SDMMC1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, SDMMC12CKSELR_REG)

SDMMC2_SEL

#define SDMMC2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 3, SDMMC12CKSELR_REG)

SPDIF_SEL

#define SPDIF_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 0, SPDIFCKSELR_REG)

SPDIFCKSELR_REG

#define SPDIFCKSELR_REG   0x640

SPI1_SEL

#define SPI1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S1CKSELR_REG)

SPI23_SEL

#define SPI23_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S23CKSELR_REG)

SPI2S1CKSELR_REG

#define SPI2S1CKSELR_REG   0x608

SPI2S23CKSELR_REG

#define SPI2S23CKSELR_REG   0x60c

SPI45CKSELR_REG

#define SPI45CKSELR_REG   0x610

SPI4_SEL

#define SPI4_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI45CKSELR_REG)

SPI5_SEL

#define SPI5_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 3, SPI45CKSELR_REG)

STGEN_SEL

#define STGEN_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 0, STGENCKSELR_REG)

STGENCKSELR_REG

#define STGENCKSELR_REG   0x660

STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x750

STM32_CLOCK_BUS_AHB4

#define STM32_CLOCK_BUS_AHB4   0x768

STM32_CLOCK_BUS_AHB5

#define STM32_CLOCK_BUS_AHB5   0x778

STM32_CLOCK_BUS_AHB6

#define STM32_CLOCK_BUS_AHB6   0x780

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x700

Bus clocks.

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x708

STM32_CLOCK_BUS_APB3

#define STM32_CLOCK_BUS_APB3   0x710

STM32_CLOCK_BUS_APB4

#define STM32_CLOCK_BUS_APB4   0x728

STM32_CLOCK_BUS_APB4_NS

#define STM32_CLOCK_BUS_APB4_NS   0x738

STM32_CLOCK_BUS_APB5

#define STM32_CLOCK_BUS_APB5   0x740

STM32_CLOCK_BUS_APB6

#define STM32_CLOCK_BUS_APB6   0x748

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_AHB6

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_APB1

STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_LSI + 1)

System clock.

Fixed clocks

STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_HSE + 1)

STM32_SRC_PLL1_P

#define STM32_SRC_PLL1_P   (STM32_SRC_HSI + 1)

PLL outputs.

STM32_SRC_PLL2_P

#define STM32_SRC_PLL2_P   (STM32_SRC_PLL1_P + 1)

STM32_SRC_PLL2_Q

#define STM32_SRC_PLL2_Q   (STM32_SRC_PLL2_P + 1)

STM32_SRC_PLL2_R

#define STM32_SRC_PLL2_R   (STM32_SRC_PLL2_Q + 1)

STM32_SRC_PLL3_P

#define STM32_SRC_PLL3_P   (STM32_SRC_PLL2_R + 1)

STM32_SRC_PLL3_Q

#define STM32_SRC_PLL3_Q   (STM32_SRC_PLL3_P + 1)

STM32_SRC_PLL3_R

#define STM32_SRC_PLL3_R   (STM32_SRC_PLL3_Q + 1)

STM32_SRC_PLL4_P

#define STM32_SRC_PLL4_P   (STM32_SRC_PLL3_R + 1)

STM32_SRC_PLL4_Q

#define STM32_SRC_PLL4_Q   (STM32_SRC_PLL4_P + 1)

STM32_SRC_PLL4_R

#define STM32_SRC_PLL4_R   (STM32_SRC_PLL4_Q + 1)

UART12CKSELR_REG

#define UART12CKSELR_REG   0x614

UART1_SEL

#define UART1_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART12CKSELR_REG)

UART2_SEL

#define UART2_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 3, UART12CKSELR_REG)

UART35_SEL

#define UART35_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART35CKSELR_REG)

UART35CKSELR_REG

#define UART35CKSELR_REG   0x618

UART4_SEL

#define UART4_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART4CKSELR_REG)

UART4CKSELR_REG

#define UART4CKSELR_REG   0x61c

UART6_SEL

#define UART6_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART6CKSELR_REG)

UART6CKSELR_REG

#define UART6CKSELR_REG   0x620

UART78_SEL

#define UART78_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART78CKSELR_REG)

UART78CKSELR_REG

#define UART78CKSELR_REG   0x624

USBCKSELR_REG

#define USBCKSELR_REG   0x650

USBOTG_SEL

#define USBOTG_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x1, 4, USBCKSELR_REG)

USBPHY_SEL

#define USBPHY_SEL

(

val

)

Value:

STM32_DT_CLOCK_SELECT((val), 0x3, 0, USBCKSELR_REG)