Zephyr API Documentation 4.0.0-rc2
A Scalable Open Source RTOS
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Macros
stm32f427_clock.h File Reference

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Macros

#define DCKCFGR_REG   0x8C
 RCC_DCKCFGR register offset.
 
#define CKDFSDM2A_SEL(val)
 Device domain clocks selection helpers.
 
#define CKDFSDM1A_SEL(val)
 
#define SAI1A_SEL(val)
 
#define SAI1B_SEL(val)
 
#define CLK48M_SEL(val)
 
#define SDMMC_SEL(val)
 
#define DSI_SEL(val)
 

Macro Definition Documentation

◆ CKDFSDM1A_SEL

#define CKDFSDM1A_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG)
STM32_DOMAIN_CLOCK
#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)
STM32 clock configuration bit field.
Definition stm32c0_clock.h:54
DCKCFGR_REG
#define DCKCFGR_REG
RCC_DCKCFGR register offset.
Definition stm32f427_clock.h:10

◆ CKDFSDM2A_SEL

#define CKDFSDM2A_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG)

Device domain clocks selection helpers.

DCKCFGR devices

◆ CLK48M_SEL

#define CLK48M_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR_REG)

◆ DCKCFGR_REG

#define DCKCFGR_REG   0x8C

RCC_DCKCFGR register offset.

◆ DSI_SEL

#define DSI_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR_REG)

◆ SAI1A_SEL

#define SAI1A_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG)

◆ SAI1B_SEL

#define SAI1B_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG)

◆ SDMMC_SEL

#define SDMMC_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR_REG)