BL704L Development Board

Overview

This board is a development platform designed for usage with Zephyr RTOS, filling in for the absence of official BL70xL development boards, it features BL704L and CH32V203. BL704L is a highly integrated 802.15.4 (Zigbee/Thread/Matter) and BLE combo chipset for IoT applications. CH32V203 is used as the interfacing chip, providing UART and JTAG conversion to USB.

Hardware

BL704L_DVK provides the following hardware components:

BL704L20Q2IW low-power RF microcontroller. 32MHz and 32.768KHz crystals are populated.
CH32V203F8U6 general purpose microcontroller.
Eight Amber-colored LEDs:
- Two connected to GPIO17 and GPIO18 of BL704L
- Five forming a line connected to PB14, PB15, PA8, PA9, and PA10 of CH32V203
- One additional LED indicating DAPLink status, connected to PA5 of CH32V203
Three Buttons:
- Reset Button for BL704L (SW1)
- Boot Select Button for BL704L (SW2, GPIO16)
- User Button (SW3, GPIO13)
FPC connector for Reflective LCD displays using 24Pin headers. A 2.13” ST7305 display is provided by default.
Pads for I2C DFN-6 sensors (CHT8315, HTU21D) and various formats of storage chips are provided.

For more information about the BouffaloLab BL704L MCU and the device:

Supported Features

The bl704l_dvk board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`bl704l_dvk/bl704l20q2iw` target

On-target memory for this board target: 56 KiB of RAM, 2 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	SiFive E24 Standard Core CPU1	`sifive,e24`
ADC	on-chip	Bouffalolab ADC1	`bflb,adc`
Bluetooth	on-chip	Bluetooth HCI for Bouffalo Lab on-chip BLE controllers1	`bflb,bt-hci`
Cache	on-chip	Bouffalo Lab L1C cache control1	`bflb,l1c`
Clock control	on-chip	Generic fixed-rate clock provider3 1	`fixed-clock`
	on-chip	Bouffalolab F32K clock1	`bflb,f32k`
	on-chip	The BL70x/L DLL1	`bflb,bl70x_l-dll`
	on-chip	Bouffalolab Root Clock Represents both FCLK and HCLK depending on their presence, which should be kept the same1	`bflb,root-clk`
	on-chip	The BCLK clock, or peripheral clock Source -> / divider -> This Clock1	`bflb,bclk`
	on-chip	BFLB Flash Clock Source -> divider -> CLK Only has settings for Bank 1 on BL61x (boot flash) at the moment1	`bflb,flash-clk`
	on-chip	Bouffalolab BL70x(L) Clock Controller1	`bflb,bl70x_l-clock-controller`
Cryptographic accelerator	on-chip	Bouffalo Lab SEC Engine TRNG (True Random Number Generator)1	`bflb,sec-eng-trng`
	on-chip	Bouffalo Lab SEC Engine SHA hardware accelerator1	`bflb,sec-eng-sha`
	on-chip	Bouffalo Lab SEC Engine AES hardware accelerator1	`bflb,sec-eng-aes`
Display	on-board	ST7305 display controller1	`sitronix,st7305`
DMA	on-chip	Bouffalo Lab DMA1	`bflb,dma`
GPIO & Headers	on-chip	Bouffalo Lab BL60x and BL70x GPIO node1	`bflb,bl60x_70x-gpio`
I2C	on-chip	Bouffalolab I2C interface1	`bflb,i2c`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	RISC-V CPU interrupt controller1	`riscv,cpu-intc`
Interrupt controller	on-chip	RISC-V Core Local Interrupt Controller CLIC Pre-Standard v0.91	`sifive,clic-draft`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
LED	on-board	Group of PWM-controlled LEDs1	`pwm-leds`
Memory controller	on-chip	Serial Flash controller1	`bflb,sf-controller`
Memory controller	on-chip	Serial Flash Controller Bank1 1	`bflb,sf-bank`
MTD	on-board	Bouffalolab Serial Flash controller Flash1	`bflb,sf-flash`
OTP memory	on-chip	BouffaloLab Efuse1	`bflb,efuse`
Pin control	on-chip	Bouffalo Lab Pinctrl node1	`bflb,pinctrl`
Power management	on-chip	Bouffalolab Power Controller1	`bflb,power-controller`
PWM	on-chip	Bouffalolab PWM 11	`bflb,pwm-1`
PWM	on-chip	Bouffalolab PWM 21	`bflb,pwm-2`
Regulator	on-chip	Bouffalolab HBN SoC (CPU, Memory, etc) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,soc-regulator`
Regulator	on-chip	Bouffalolab HBN AON (Always ON section) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,aon-regulator`
Sensors	on-chip	Bouffalo Lab internal die temperature sensor (TSEN)1	`bflb,tsen`
Sensors	on-board	Measurement Specialties HTU21D Humidity and Temperature Sensor1	`meas,htu21d`
Serial controller	on-chip	Bouffalo Lab UART1	`bflb,uart`
SPI	on-chip	Bouffalolab SPI1	`bflb,spi`
SRAM	on-chip	Generic on-chip SRAM3	`mmio-sram`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`
Watchdog	on-chip	Bouffalo Lab Watchdog Timer1	`bflb,wdt`

System Clock

The Device is configured to run at max speed (128MHz).

Serial Port

The bl704l_dvk board uses ACM0 as default serial port.

Programming and Debugging

The bl704l_dvk board supports the runners and associated west commands listed below.

	flash	debug	debugserver	rtt	attach
bflb_mcu_tool	✅ (default)
openocd	✅	✅ (default)	✅	✅	✅

Samples

Build the Zephyr kernel and the Hello World sample application:

# From the root of the zephyr repository
west build -b bl704l_dvk samples/hello_world
west flash

Run your favorite terminal program to listen for output. Under Linux the terminal should be /dev/ttyACM0. For example:
```
$ screen /dev/ttyACM0 115200
```
Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Then, press and release RST button
```
*** Booting Zephyr OS build v4.4 ***
Hello World! bl704l_dvk/bl704l20q2iw
```

Congratulations, you have bl704l_dvk configured and running Zephyr.