Go to the source code of this file.
◆ AES_INTR_SOURCE
#define AES_INTR_SOURCE 60 |
◆ APB_ADC_INTR_SOURCE
#define APB_ADC_INTR_SOURCE 48 |
◆ ASSIST_DEBUG_INTR_SOURCE
#define ASSIST_DEBUG_INTR_SOURCE 11 |
◆ BLE_SEC_INTR_SOURCE
#define BLE_SEC_INTR_SOURCE 20 |
◆ BLE_TIMER_INTR_SOURCE
#define BLE_TIMER_INTR_SOURCE 19 |
◆ BT_BB_INTR_SOURCE
#define BT_BB_INTR_SOURCE 16 |
◆ BT_BB_NMI_INTR_SOURCE
#define BT_BB_NMI_INTR_SOURCE 17 |
◆ BT_MAC_INTR_SOURCE
#define BT_MAC_INTR_SOURCE 15 |
◆ CACHE_INTR_SOURCE
#define CACHE_INTR_SOURCE 13 |
◆ COEX_INTR_SOURCE
#define COEX_INTR_SOURCE 18 |
◆ CPU_PERI_TIMEOUT_INTR_SOURCE
#define CPU_PERI_TIMEOUT_INTR_SOURCE 14 |
◆ DMA_IN_CH0_INTR_SOURCE
#define DMA_IN_CH0_INTR_SOURCE 53 |
◆ DMA_IN_CH1_INTR_SOURCE
#define DMA_IN_CH1_INTR_SOURCE 54 |
◆ DMA_IN_CH2_INTR_SOURCE
#define DMA_IN_CH2_INTR_SOURCE 55 |
◆ DMA_OUT_CH0_INTR_SOURCE
#define DMA_OUT_CH0_INTR_SOURCE 56 |
◆ DMA_OUT_CH1_INTR_SOURCE
#define DMA_OUT_CH1_INTR_SOURCE 57 |
◆ DMA_OUT_CH2_INTR_SOURCE
#define DMA_OUT_CH2_INTR_SOURCE 58 |
◆ ECC_INTR_SOURCE
#define ECC_INTR_SOURCE 63 |
◆ ECDSA_INTR_SOURCE
#define ECDSA_INTR_SOURCE 64 |
◆ EFUSE_INTR_SOURCE
#define EFUSE_INTR_SOURCE 1 |
◆ ESP_INTR_FLAG_SHARED
#define ESP_INTR_FLAG_SHARED (1 << 8) /* Interrupt can be shared between ISRs */ |
◆ FROM_CPU_INTR0_SOURCE
#define FROM_CPU_INTR0_SOURCE 7 |
◆ FROM_CPU_INTR1_SOURCE
#define FROM_CPU_INTR1_SOURCE 8 |
◆ FROM_CPU_INTR2_SOURCE
#define FROM_CPU_INTR2_SOURCE 9 |
◆ FROM_CPU_INTR3_SOURCE
#define FROM_CPU_INTR3_SOURCE 10 |
◆ GPIO_INTR_SOURCE
#define GPIO_INTR_SOURCE 22 |
◆ GPIO_NMI_SOURCE
#define GPIO_NMI_SOURCE 23 |
◆ GSPI2_INTR_SOURCE
#define GSPI2_INTR_SOURCE 59 |
◆ HP_APM_M0_INTR_SOURCE
#define HP_APM_M0_INTR_SOURCE 26 |
◆ HP_APM_M1_INTR_SOURCE
#define HP_APM_M1_INTR_SOURCE 27 |
◆ HP_APM_M2_INTR_SOURCE
#define HP_APM_M2_INTR_SOURCE 28 |
◆ HP_APM_M3_INTR_SOURCE
#define HP_APM_M3_INTR_SOURCE 29 |
◆ HP_PERI_TIMEOUT_INTR_SOURCE
#define HP_PERI_TIMEOUT_INTR_SOURCE 25 |
◆ I2C_EXT0_INTR_SOURCE
#define I2C_EXT0_INTR_SOURCE 39 |
◆ I2C_EXT1_INTR_SOURCE
#define I2C_EXT1_INTR_SOURCE 40 |
◆ I2S1_INTR_SOURCE
#define I2S1_INTR_SOURCE 31 |
◆ IRQ_DEFAULT_PRIORITY
#define IRQ_DEFAULT_PRIORITY 0 |
◆ LEDC_INTR_SOURCE
#define LEDC_INTR_SOURCE 35 |
◆ LP_APM_M0_INTR_SOURCE
#define LP_APM_M0_INTR_SOURCE 6 |
◆ LP_BLE_TIMER_INTR_SOURCE
#define LP_BLE_TIMER_INTR_SOURCE 3 |
◆ LP_PERI_TIMEOUT_INTR_SOURCE
#define LP_PERI_TIMEOUT_INTR_SOURCE 5 |
◆ LP_RTC_TIMER_INTR_SOURCE
#define LP_RTC_TIMER_INTR_SOURCE 2 |
◆ LP_WDT_INTR_SOURCE
#define LP_WDT_INTR_SOURCE 4 |
◆ MAX_INTR_SOURCE
#define MAX_INTR_SOURCE 65 |
◆ MCPWM0_INTR_SOURCE
#define MCPWM0_INTR_SOURCE 49 |
◆ MSPI_INTR_SOURCE
#define MSPI_INTR_SOURCE 30 |
◆ PARL_IO_RX_INTR_SOURCE
#define PARL_IO_RX_INTR_SOURCE 52 |
◆ PARL_IO_TX_INTR_SOURCE
#define PARL_IO_TX_INTR_SOURCE 51 |
◆ PAU_INTR_SOURCE
#define PAU_INTR_SOURCE 24 |
◆ PCNT_INTR_SOURCE
#define PCNT_INTR_SOURCE 50 |
◆ PMU_INTR_SOURCE
#define PMU_INTR_SOURCE 0 |
◆ RMT_INTR_SOURCE
#define RMT_INTR_SOURCE 38 |
◆ RSA_INTR_SOURCE
#define RSA_INTR_SOURCE 62 |
◆ SHA_INTR_SOURCE
#define SHA_INTR_SOURCE 61 |
◆ SYSTIMER_TARGET0_EDGE_INTR_SOURCE
#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 45 |
◆ SYSTIMER_TARGET1_EDGE_INTR_SOURCE
#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 46 |
◆ SYSTIMER_TARGET2_EDGE_INTR_SOURCE
#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 47 |
◆ TG0_T0_LEVEL_INTR_SOURCE
#define TG0_T0_LEVEL_INTR_SOURCE 41 |
◆ TG0_WDT_LEVEL_INTR_SOURCE
#define TG0_WDT_LEVEL_INTR_SOURCE 42 |
◆ TG1_T0_LEVEL_INTR_SOURCE
#define TG1_T0_LEVEL_INTR_SOURCE 43 |
◆ TG1_WDT_LEVEL_INTR_SOURCE
#define TG1_WDT_LEVEL_INTR_SOURCE 44 |
◆ TRACE_INTR_SOURCE
#define TRACE_INTR_SOURCE 12 |
◆ TWAI0_INTR_SOURCE
#define TWAI0_INTR_SOURCE 36 |
◆ UART0_INTR_SOURCE
#define UART0_INTR_SOURCE 33 |
◆ UART1_INTR_SOURCE
#define UART1_INTR_SOURCE 34 |
◆ UHCI0_INTR_SOURCE
#define UHCI0_INTR_SOURCE 32 |
◆ USB_SERIAL_JTAG_INTR_SOURCE
#define USB_SERIAL_JTAG_INTR_SOURCE 37 |
◆ ZB_MAC_INTR_SOURCE
#define ZB_MAC_INTR_SOURCE 21 |