VAR-SOM-MX8M-PLUS

Board Overview

VAR-SOM-MX8M-PLUS

Name:

imx8mp_var_som

Vendor:

Variscite Ltd.

Architecture:

arm, arm64

SoC:

mimx8ml8

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Overview

Variscite’s VAR-SOM-MX8M-PLUS System on Module (SoM) is based on the i.MX 8M Plus family, which is a set of NXP products built to achieve both high performance and low power consumption and relies on a powerful, fully coherent core complex based on a quad Cortex®-A53 cluster and Cortex®-M7 low-power coprocessor, audio digital signal processor, machine learning and graphics accelerators.

Zephyr OS is ported to run on either the Cortex®-A53 or the Cortex®-M7.

Specs Summary

• CPU

  • NXP i.MX8M Plus:

  • Up to 4x Cortex®-A53 @ 1.8GHz

  • 1x Cortex®-M7 @ 800 MHz

  • 1x NPU 2.3 TOPS

• Memory

  • Up to 8GB LPDDR4 RAM @ 2000MHz

  • 8-bit up to 128GB eMMC boot and storage

• GPU

  • 3D: Vivante™ GC7000UltraLite (2 shaders) OpenGL ES 3.0, OpenCL1.2, Vulkan

  • 2D: Vivante™ GC520L

• NPU (Neural Processing Unit)

  • 2.3 TOPS Neural Network performance

• Display

  • 2x LVDS interface 4-lane each up to 1080p60

  • HDMI 2.0a up to 4Kp30

  • 1x MIPI DSI with up to 4 data lanes 1080p60

• Network

  • 2x 10/100/1000 Mbit/s Ethernet Interface

  • Certified Wi-Fi 6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4

  • Bluetooth/BLE 5.4

• Camera

  • Up to 2x MIPI CSI – CMOS Serial camera Interface 4 lanes

  • 375 Mpixel/s HDR ISP (Image Sensor Processor)

• Audio

  • Headphones

  • Microphone: Digital, Analog (stereo)

  • 6x I2S(SAI), S/PDIF RX TX, PDM 8CH, Line In/Out

• USB

  • 2x USB 3.0/2.0 Host/Device

• Serial interfaces

  • SPI: x3

  • I2C: x5

  • UART: x4, up to 5 Mbps

  • CAN: x2

• Temperature range

  • -40°C to 85°C

More information about the SoM can be found at the Variscite Wiki and Variscite website.

Supported Features

The imx8mp_var_som board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

imx8mp_var_som

/

mimx8ml8/a53mimx8ml8/m7mimx8ml8/m7/ddr

imx8mp_var_som/mimx8ml8/a53 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A53 CPU1 3	arm,cortex-a53
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
Ethernet	on-chip	NXP ENET1G IP Module1	nxp,enet1g
	on-chip	NXP ENET MAC/L2 Device1	nxp,enet-mac
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1	nxp,enet-ptp-clock
GPIO & Headers	on-chip	i.MX GPIO1 4	nxp,imx-gpio
I2C	on-chip	NXP II2C6	nxp,ii2c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	arm,gic-v3
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
MDIO	on-chip	NXP ENET MDIO Features1	nxp,enet-mdio
Miscellaneous	on-chip	NXP i.MX Resource Domain Controller (RDC)1	nxp,rdc
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 1	nxp,imx-iuart
Timer	on-chip	NXP MCUX General-Purpose Timer (GPT)2	nxp,imx-gpt
	on-chip	per-core ARM architected timer1	arm,armv8-timer

imx8mp_var_som/mimx8ml8/m7 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	arm,cortex-m7
ARM architecture	on-chip	i.MX ITCM (Instruction Tightly Coupled Memory)1	nxp,imx-itcm
	on-chip	i.MX DTCM (Data Tightly Coupled Memory)1	nxp,imx-dtcm
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
GPIO & Headers	on-chip	i.MX GPIO1 4	nxp,imx-gpio
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	arm,v7m-nvic
IPM	on-chip	i.MX Messaging Unit1	nxp,imx-mu
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
MMU / MPU	on-chip	ARMv7-M Memory Protection Unit (MPU)1	arm,armv7m-mpu
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 1	nxp,imx-iuart
SPI	on-chip	NXP i.MX ECSPI controller3	nxp,imx-ecspi
Timer	on-chip	ARMv7-M System Tick1	arm,armv7m-systick

imx8mp_var_som/mimx8ml8/m7/ddr target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M7 CPU1	arm,cortex-m7
ARM architecture	on-chip	i.MX ITCM (Instruction Tightly Coupled Memory)1	nxp,imx-itcm
	on-chip	i.MX DTCM (Data Tightly Coupled Memory)1	nxp,imx-dtcm
Clock control	on-chip	i.MX CCM (Clock Controller Module) IP node1	nxp,imx-ccm
GPIO & Headers	on-chip	i.MX GPIO1 4	nxp,imx-gpio
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARMv7-M NVIC (Nested Vectored Interrupt Controller)1	arm,v7m-nvic
IPM	on-chip	i.MX Messaging Unit1	nxp,imx-mu
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
MMU / MPU	on-chip	ARMv7-M Memory Protection Unit (MPU)1	arm,armv7m-mpu
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx8mp-pinctrl
Serial controller	on-chip	This binding gives a base representation of the NXP iMX IUART1 1	nxp,imx-iuart
SPI	on-chip	NXP i.MX ECSPI controller3	nxp,imx-ecspi
Timer	on-chip	ARMv7-M System Tick1	arm,armv7m-systick

Note

It is recommended to disable peripherals used by the M7 core on the Linux host.

Devices

System Clock

This board configuration uses a system clock frequency of 8 MHz.

The M7 core is configured to run at an 800 MHz clock speed.

Serial Port

This board configuration uses a single serial communication channel with the CPU’s UART4.

Programming and Debugging (A53)

Copy the compiled zephyr.bin to the boot directory of the SD card and plug the SD card into the board. Power it up and stop the U-Boot execution at prompt.

Use U-Boot to load and run zephyr.bin on the Cortex-A53:

load mmc $mmcdev:$mmcpart $loadaddr /boot/zephyr.bin
dcache flush; icache flush; go $loadaddr

Use this configuration to run basic Zephyr applications and kernel tests, for example, with the Hello World sample:

# From the root of the zephyr repository
west build -b imx8mp_var_som/mimx8ml8/a53 samples/hello_world

This will build an image with the hello_world sample app. When loaded and executed it will display the following ram console output:

*** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa ***
Hello World! imx8mp_var_som/mimx8ml8/a53

Programming and Debugging (M7)

The imx8mp_var_som board supports the runners and associated west commands listed below.

	flash	debug	debugserver	rtt	attach
jlink	✅ (default)	✅ (default)	✅	✅	✅

The VAR-SOM-MX8M-PLUS don’t have QSPI flash for the M7, and it needs to be started by the A53 core. The A53 core is responsible to load the M7 binary application into the RAM, put the M7 in reset, set the M7 Program Counter and Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at bootloader level or after the Linux system has booted.

The M7 can use up to 3 different RAMs (currently, only two configurations are supported: ITCM and DDR). These are the memory mapping for A53 and M7:

Region	Cortex-A53	Cortex-M7 (System Bus)	Cortex-M7 (Code Bus)	Size
OCRAM	0x00900000-0x0098FFFF	0x20200000-0x2028FFFF	0x00900000-0x0098FFFF	576KB
DTCM	0x00800000-0x0081FFFF	0x20000000-0x2001FFFF		128KB
ITCM	0x007E0000-0x007FFFFF		0x00000000-0x0001FFFF	128KB
OCRAM_S	0x00180000-0x00188FFF	0x20180000-0x20188FFF	0x00180000-0x00188FFF	36KB
DDR	0x80000000-0x803FFFFF	0x7B200000-0x7B3FFFFF	0x7B000000-0x7B1FFFFF	2MB

For more information about memory mapping see the i.MX 8M Applications Processor Reference Manual (section 2.1 to 2.3)

At compilation time you have to choose which RAM will be used. This configuration is done based on board name (e.g. imx8mp_var_som/mimx8ml8/m7 for ITCM and imx8mp_var_som/mimx8ml8/m7/ddr for DDR).

There are two methods to load M7 Core images: U-Boot command and Linux remoteproc.

Load and Run M7 Zephyr Image from U-Boot

Load and run Zephyr on M7 from A53 using U-Boot by copying the compiled zephyr.bin to the boot directory of the SD card and plug the SD card into the board. Power it up and stop the U-Boot execution at prompt.

Load the M7 binary onto the desired memory and start its execution using:

ITCM

load mmc 1:1 0x48000000 /boot/zephyr.bin
cp.b 0x48000000 0x7e0000 20000
bootaux 0x7e0000

DDR

load mmc 1:1 0x7b000000 /boot/zephyr.bin
dcache flush
bootaux 0x7b000000

Load and Run M7 Zephyr Image by using Linux remoteproc

Transfer built binaries zephyr.bin and zephyr.elf to the SoM’s /boot and /lib/firmware respectively using scp or through an USB drive.

It is possible to execute Zephyr binaries using Variscite remoteproc scripts made for MCUXpresso binaries:

root@imx8mp-var-dart:~# /etc/remoteproc/variscite-rproc-linux -f /lib/firmware/zephyr.elf
[  212.888118] remoteproc remoteproc0: powering up imx-rproc
[  212.899215] remoteproc remoteproc0: Booting fw image zephyr.elf, size 515836
[  212.912070] remoteproc remoteproc0: No resource table in elf
[  213.444675] remoteproc remoteproc0: remote processor imx-rproc is now up

Which should yield the following result on the UART4 serial console:

*** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa ***
Hello World! imx8mp_var_som/mimx8ml8/m7

If the device tree dedicated to be used with Cortex-M7 applications is not being currently used, the script will give instructions on how to do so:

Error: /sys/class/remoteproc/remoteproc0 not found.
Please enable remoteproc driver.
Most likely you need to use the correct device tree, for example:
fw_setenv fdt_file imx8mp-var-som-symphony-m7.dtb && reboot

You can also configure U-Boot to load firmware on boot:

root@imx8mp-var-dart:~# /etc/remoteproc/variscite-rproc-u-boot -f /boot/zephyr.bin
Configuring for TCM memory
+ fw_setenv m7_addr 0x7E0000
+ fw_setenv fdt_file imx8mp-var-som-symphony-m7.dtb
+ fw_setenv use_m7 yes
+ fw_setenv m7_bin zephyr.bin

Finished: Please reboot, the m7 firmware will run during U-Boot

For more information about Variscite remoteproc scripts and general Cortex-M7 support, visit Variscite Wiki.

Debugging

VAR-SOM-MX8M-PLUS board can be debugged by connecting an external JLink JTAG debugger to the 14-pin header on the top left side of the SoM and to the PC. Then the application can be debugged using the usual way.

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b imx8mp_var_som/mimx8ml8/m7 samples/hello_world
west debug

Open a serial terminal, step through the application in your debugger, and you should see the following message in the terminal:

*** Booting Zephyr OS build v4.0.0-3113-g5aeda6fe7dfa ***
Hello World! imx8mp_var_som/mimx8ml8/m7

References

• Variscite Wiki

• Variscite website

• i.MX 8M Applications Processor Reference Manual