PSOC™ Edge E84 AI Evaluation Kit

Overview

The KIT_PSE84_AI is an evaluation kit based on the PSOC™ Edge E84 family, featuring a PSE846GPS2DBZC4A microcontroller with an Arm® Cortex®-M33 core at 200 MHz, an Arm® Cortex®-M55 core at 400 MHz, and an Arm® Ethos™-U55 NPU. It is designed for machine learning, wearables, and IoT applications.

Key features include 512-Mb QSPI NOR flash, 128-Mb Octal HYPERRAM™, AIROC™ CYW55513-based Wi-Fi + Bluetooth® connectivity (LBEE5HY2FY module), a rich sensor suite (6-axis IMU, magnetometer, barometric pressure, humidity, radar), MIPI-DSI display interface, analog and digital microphones, and an OV7675 DVP camera module.

The board includes an onboard KitProg3 programmer/debugger with USB Type-C connectivity, expansion IO header, and Raspberry Pi compatible MIPI-DSI display support.

Boot Flow

The Cortex®-M33 is the boot core. The Cortex®-M55 stays in reset until an application running on the M33 releases it.

Reset
  -> Extended boot (Infineon, stored in RRAM), reads the boot pin
       (HIGH by default: first image in external flash)
  -> CM33 Secure image (Zephyr, or TF-M when using the /ns target)
       -> CM33 application
       -> optional: releases the CM55
            -> CM55 application

The first image run by the extended boot must be in MCUboot image format. The build produces this format automatically; see Secure Boot for details.

Board Targets

Build Target	What runs	Sysbuild	Flashed file
`kit_pse84_ai/pse846gps2dbzc4a/m33`	Zephyr on CM33 Secure. The CM55 is not started.	No	`zephyr.signed.hex`
`kit_pse84_ai/pse846gps2dbzc4a/m33/ns`	TF-M on CM33 Secure, Zephyr on CM33 Non-Secure.	No	`tfm_merged.hex`
`kit_pse84_ai/pse846gps2dbzc4a/m55`	Zephyr on CM55. A minimal CM33 image (`enable_cm55`) is built and flashed with it to start the CM55.	Yes	Both images

There are two ways to run an application on the CM55:

Standalone CM55 (m55 target with --sysbuild): the CM55 runs the application and the CM33 only starts it. This is the usual choice.
CM55 with TF-M (m33/ns and m55 built separately, without sysbuild): the CM55 uses the TF-M secure services running on the CM33. See TF-M Multicore Support.

Hardware

SoC: PSOC™ Edge E84 (PSE846GPS2DBZC4A)
CPUs: Arm® Cortex®-M33 at 200 MHz (boot core), Arm® Cortex®-M55 at 400 MHz
NPU: Arm® Ethos™-U55
Flash: 512-Mb QSPI NOR flash
RAM: 128-Mb Octal HYPERRAM
Wireless: LBEE5HY2FY module — Wi-Fi + Bluetooth® (AIROC CYW55513)
Sensors: 6-axis IMU, 3-axis magnetometer, barometric pressure, humidity, radar
Display: MIPI-DSI (Raspberry Pi compatible)
Audio: Analog and digital microphones
USB: Type-C (device)
Expansion: Expansion IO header
User I/O: User LEDs and user button
Security: Arm® TrustZone®-M, secure enclave with crypto accelerators
Debug: Onboard KitProg3 (SWD + UART bridge)

For more information about the PSOC™ Edge E84 and KIT_PSE84_AI:

Kit Contents

PSOC™ Edge E84 AI Evaluation Kit board
OV7675 DVP camera module

Supported Features

The kit_pse84_ai board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`kit_pse84_ai/pse846gps2dbzc4a/m33` target

On-target memory for this board target: 132 KiB of RAM, 64 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33 CPU1	`arm,cortex-m33`
ADC	on-chip	PSOC Edge AutAnalog SAR ADC1	`infineon,autanalog-sar-adc`
ARM architecture	on-chip	Infineon Serial Communication Blocks (SCB) node9	`infineon,scb`
Audio	on-chip	Infineon PDM (Pulse Density Modulation) Controller1	`infineon,pdm`
Bluetooth	on-board	Connectivity chip that uses Infineon Bluetooth Host Controller Interface UART driver1	`infineon,bt-hci-uart`
CAN	on-chip	Infineon CAN FD controller wrapper. 1	`infineon,canfd-controller`
CAN	on-chip	Infineon MCAN Driver2	`infineon,can`
Clock control	on-chip	Generic fixed-rate clock provider5	`infineon,fixed-clock`
	on-chip	Generic fixed-rate clock provider20	`infineon,fixed-factor-clock`
	on-chip	infineon peripheral divider3 23	`infineon,peri-div`
Comparator	on-chip	Infineon Low Power Comparator (LPComp) for CAT1 family1	`infineon,lp-comp`
Comparator	on-chip	Infineon LPComp channel node (child of infineon,lp-comp)2	`infineon,lp-comp-channel`
Counter	on-chip	Infineon TCPWM counter32	`infineon,tcpwm-counter`
Cryptographic accelerator	on-chip	Infineon MXCRYPTO True Random Number Generator1	`infineon,mxcrypto-trng`
Cryptographic accelerator	on-chip	Infineon MXCRYPTO crypto engine (AES / SHA)1	`infineon,mxcrypto-crypto`
DAC	on-chip	PSOC Edge AutAnalog CT DAC2	`infineon,autanalog-ctdac`
DMA	on-chip	Infineon CAT1 DMA2	`infineon,dma`
DMA	on-chip	Infineon M-DMA1	`infineon,mdma`
Flash controller	on-board	Infineon CAT1 QSPI flash controller1	`infineon,qspi-flash`
GPIO & Headers	on-chip	Infineon GPIO Port11 11	`infineon,gpio`
I2C	on-chip	Infineon CAT1 I2C driver1	`infineon,i2c`
I2S	on-chip	Infineon I2S Controller2	`infineon,i2s`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v8m-nvic`
IPC	on-chip	Infineon inter-processor communication (IPC) instance2	`infineon,ipc`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Multi-Function Device	on-chip	Infineon MXCRYPTO multi-function device1	`infineon,mxcrypto`
	on-chip	Infineon AutAnalog (Autonomous Analog) Multi-Function Device1	`infineon,autanalog`
	on-chip	Infineon AutAnalog Continuous Time Block (CTB) MFD2	`infineon,autanalog-ctb`
	on-chip	Infineon AutAnalog Programmable Reference Block (PRB) MFD1	`infineon,autanalog-prb`
	on-chip	Infineon AutAnalog Programmable Threshold Comparator (PTComp) MFD1	`infineon,autanalog-ptcomp`
MTD	on-chip	Flash node4	`soc-nv-flash`
Pin control	on-chip	Infineon CAT1 Pinctrl Container1	`infineon,pinctrl`
PWM	on-chip	Infineon TCPWM PWM32	`infineon,tcpwm-pwm`
RTC	on-chip	Infineon CAT1 family RTC device1	`infineon,rtc`
SDHC	on-chip	Infineon CAT1 SDHC/SDIO controller2	`infineon,sdhc-sdio`
Sensors	on-board	Sensirion SHT4x humidity and temperature sensor1	`sensirion,sht4x`
	on-board	The BMI270 is an inertial measurement unit1	`bosch,bmi270`
	on-board	Infineon DPS310 temperature and pressure sensor1	`infineon,dps310`
Serial controller	on-chip	Infineon CAT1 UART2	`infineon,uart`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	Infineon low power timer1 1	`infineon,lp-timer`
	on-chip	Infineon TCPWM Timer32	`infineon,tcpwm`
	on-chip	ARMv8-M System Tick1	`arm,armv8m-systick`
USB	on-chip	Infineon USBHS1	`infineon,usbhs`
Watchdog	on-chip	Infineon CAT1 Watchdog1	`infineon,watchdog`

`kit_pse84_ai/pse846gps2dbzc4a/m33/ns` target

On-target memory for this board target: 256 KiB of RAM, 64 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M33 CPU1	`arm,cortex-m33`
ADC	on-chip	PSOC Edge AutAnalog SAR ADC1	`infineon,autanalog-sar-adc`
ARM architecture	on-chip	Infineon Serial Communication Blocks (SCB) node9	`infineon,scb`
ARM architecture	on-chip	Infineon PSE84 frontend of Arm Ethos-U NPU1	`infineon,edge-npu`
Audio	on-chip	Infineon PDM (Pulse Density Modulation) Controller1	`infineon,pdm`
Bluetooth	on-board	Connectivity chip that uses Infineon Bluetooth Host Controller Interface UART driver1	`infineon,bt-hci-uart`
CAN	on-chip	Infineon CAN FD controller wrapper. 1	`infineon,canfd-controller`
CAN	on-chip	Infineon MCAN Driver2	`infineon,can`
Clock control	on-chip	Generic fixed-rate clock provider5	`infineon,fixed-clock`
	on-chip	Generic fixed-rate clock provider20	`infineon,fixed-factor-clock`
	on-chip	infineon peripheral divider3 23	`infineon,peri-div`
Comparator	on-chip	Infineon Low Power Comparator (LPComp) for CAT1 family1	`infineon,lp-comp`
Comparator	on-chip	Infineon LPComp channel node (child of infineon,lp-comp)2	`infineon,lp-comp-channel`
Counter	on-chip	Infineon TCPWM counter32	`infineon,tcpwm-counter`
Cryptographic accelerator	on-chip	Infineon MXCRYPTO True Random Number Generator1	`infineon,mxcrypto-trng`
Cryptographic accelerator	on-chip	Infineon MXCRYPTO crypto engine (AES / SHA)1	`infineon,mxcrypto-crypto`
DAC	on-chip	PSOC Edge AutAnalog CT DAC2	`infineon,autanalog-ctdac`
DMA	on-chip	Infineon CAT1 DMA2	`infineon,dma`
DMA	on-chip	Infineon M-DMA1	`infineon,mdma`
Flash controller	on-chip	Infineon CAT1 RRAM controller1	`infineon,rram-controller`
Flash controller	on-board	Infineon CAT1 QSPI flash controller1	`infineon,qspi-flash`
GPIO & Headers	on-chip	Infineon GPIO Port11 11	`infineon,gpio`
I2C	on-chip	Infineon CAT1 I2C driver1	`infineon,i2c`
I2S	on-chip	Infineon I2S Controller2	`infineon,i2s`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv8-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v8m-nvic`
IPC	on-chip	Infineon inter-processor communication (IPC) instance2	`infineon,ipc`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Multi-Function Device	on-chip	Infineon MXCRYPTO multi-function device1	`infineon,mxcrypto`
	on-chip	Infineon AutAnalog (Autonomous Analog) Multi-Function Device1	`infineon,autanalog`
	on-chip	Infineon AutAnalog Continuous Time Block (CTB) MFD2	`infineon,autanalog-ctb`
	on-chip	Infineon AutAnalog Programmable Threshold Comparator (PTComp) MFD1	`infineon,autanalog-ptcomp`
	on-chip	Infineon AutAnalog Programmable Reference Block (PRB) MFD1	`infineon,autanalog-prb`
MTD	on-chip	Flash node4	`soc-nv-flash`
Pin control	on-chip	Infineon CAT1 Pinctrl Container1	`infineon,pinctrl`
PWM	on-chip	Infineon TCPWM PWM32	`infineon,tcpwm-pwm`
RTC	on-chip	Infineon CAT1 family RTC device1	`infineon,rtc`
SDHC	on-chip	Infineon CAT1 SDHC/SDIO controller2	`infineon,sdhc-sdio`
Sensors	on-board	Sensirion SHT4x humidity and temperature sensor1	`sensirion,sht4x`
	on-board	The BMI270 is an inertial measurement unit1	`bosch,bmi270`
	on-board	Infineon DPS310 temperature and pressure sensor1	`infineon,dps310`
Serial controller	on-chip	Infineon CAT1 UART2	`infineon,uart`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	Infineon low power timer1 1	`infineon,lp-timer`
	on-chip	Infineon TCPWM Timer32	`infineon,tcpwm`
	on-chip	ARMv8-M System Tick1	`arm,armv8m-systick`
USB	on-chip	Infineon USBHS1	`infineon,usbhs`
Watchdog	on-chip	Infineon CAT1 Watchdog1	`infineon,watchdog`

`kit_pse84_ai/pse846gps2dbzc4a/m55` target

On-target memory for this board target: 256 KiB of RAM, 64 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-M55 CPU1	`arm,cortex-m55`
ADC	on-chip	PSOC Edge AutAnalog SAR ADC1	`infineon,autanalog-sar-adc`
ARM architecture	on-chip	Infineon Serial Communication Blocks (SCB) node9	`infineon,scb`
ARM architecture	on-chip	Infineon PSE84 frontend of Arm Ethos-U NPU1	`infineon,edge-npu`
Audio	on-chip	Infineon PDM (Pulse Density Modulation) Controller1	`infineon,pdm`
Bluetooth	on-board	Connectivity chip that uses Infineon Bluetooth Host Controller Interface UART driver1	`infineon,bt-hci-uart`
CAN	on-chip	Infineon CAN FD controller wrapper. 1	`infineon,canfd-controller`
CAN	on-chip	Infineon MCAN Driver2	`infineon,can`
Clock control	on-chip	Generic fixed-rate clock provider2 3	`infineon,fixed-clock`
	on-chip	Generic fixed-rate clock provider20	`infineon,fixed-factor-clock`
	on-chip	infineon peripheral divider4 22	`infineon,peri-div`
Comparator	on-chip	Infineon Low Power Comparator (LPComp) for CAT1 family1	`infineon,lp-comp`
Comparator	on-chip	Infineon LPComp channel node (child of infineon,lp-comp)2	`infineon,lp-comp-channel`
Counter	on-chip	Infineon TCPWM counter32	`infineon,tcpwm-counter`
Cryptographic accelerator	on-chip	Infineon MXCRYPTO True Random Number Generator1	`infineon,mxcrypto-trng`
Cryptographic accelerator	on-chip	Infineon MXCRYPTO crypto engine (AES / SHA)1	`infineon,mxcrypto-crypto`
DAC	on-chip	PSOC Edge AutAnalog CT DAC2	`infineon,autanalog-ctdac`
DMA	on-chip	Infineon CAT1 DMA2	`infineon,dma`
DMA	on-chip	Infineon M-DMA1	`infineon,mdma`
Flash controller	on-chip	Infineon CAT1 RRAM controller1	`infineon,rram-controller`
Flash controller	on-board	Infineon CAT1 QSPI flash controller1	`infineon,qspi-flash`
GPIO & Headers	on-chip	Infineon GPIO Port13 9	`infineon,gpio`
I2C	on-chip	Infineon CAT1 I2C driver1	`infineon,i2c`
I2S	on-chip	Infineon I2S Controller2	`infineon,i2s`
Input	on-board	Group of GPIO-bound input keys1	`gpio-keys`
Interrupt controller	on-chip	ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)1	`arm,v8.1m-nvic`
IPC	on-chip	Infineon inter-processor communication (IPC) instance2	`infineon,ipc`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
Multi-Function Device	on-chip	Infineon MXCRYPTO multi-function device1	`infineon,mxcrypto`
	on-chip	Infineon AutAnalog (Autonomous Analog) Multi-Function Device1	`infineon,autanalog`
	on-chip	Infineon AutAnalog Continuous Time Block (CTB) MFD2	`infineon,autanalog-ctb`
	on-chip	Infineon AutAnalog Programmable Threshold Comparator (PTComp) MFD1	`infineon,autanalog-ptcomp`
	on-chip	Infineon AutAnalog Programmable Reference Block (PRB) MFD1	`infineon,autanalog-prb`
MTD	on-chip	Flash node3 1	`soc-nv-flash`
Pin control	on-chip	Infineon CAT1 Pinctrl Container1	`infineon,pinctrl`
PWM	on-chip	Infineon TCPWM PWM32	`infineon,tcpwm-pwm`
RTC	on-chip	Infineon CAT1 family RTC device1	`infineon,rtc`
SDHC	on-chip	Infineon CAT1 SDHC/SDIO controller1 1	`infineon,sdhc-sdio`
Sensors	on-board	Sensirion SHT4x humidity and temperature sensor1	`sensirion,sht4x`
	on-board	The BMI270 is an inertial measurement unit1	`bosch,bmi270`
	on-board	Infineon DPS310 temperature and pressure sensor1	`infineon,dps310`
Serial controller	on-chip	Infineon CAT1 UART2	`infineon,uart`
SRAM	on-chip	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	Infineon low power timer1 1	`infineon,lp-timer`
	on-chip	Infineon TCPWM Timer32	`infineon,tcpwm`
	on-chip	ARMv8.1-M System Tick1	`arm,armv8.1m-systick`
USB	on-chip	Infineon USBHS1	`infineon,usbhs`
Watchdog	on-chip	Infineon CAT1 Watchdog1	`infineon,watchdog`
Wi-Fi	on-board	AIROC Wi-Fi Connectivity1	`infineon,airoc-wifi`

Connections and IOs

Pin	Function	Usage
P6.7	SCB2 UART TX	Console TX (`uart2`)
P6.5	SCB2 UART RX	Console RX (`uart2`)
P10.1	SCB4 UART TX	BT HCI TX (`uart4`)
P10.0	SCB4 UART RX	BT HCI RX (`uart4`)
P10.3	SCB4 UART RTS	BT HCI RTS (`uart4`)
P10.2	SCB4 UART CTS	BT HCI CTS (`uart4`)
P10.7	GPIO	LED0 (active high)
P10.5	GPIO	LED1 (active high)
P20.6	GPIO	RGB LED red (active high)
P20.4	GPIO	RGB LED green (active high)
P20.5	GPIO	RGB LED blue (active high)
P7.0	GPIO	User button SW1, `sw0` alias (active low, pull-up)

Serial Port

All targets use SCB2 (uart2) for the console and shell. It is routed through the KitProg3 USB-UART bridge. Default settings are 115200 8N1. When both cores run Zephyr, their output shares this UART.

The Bluetooth HCI UART is SCB4 (uart4), with hardware flow control (RTS/CTS), connected to the LBEE5HY2FY module.

System Clock

The PSOC™ Edge E84 has 14 high-frequency clocks (CLK_HF0 to CLK_HF13), configured by the CM33 image. The ones most relevant to applications are:

CLK_HF0: 200 MHz, CM33 core and system clock
CLK_HF1: 400 MHz, CM55 core

Programming and Debugging

The kit_pse84_ai board supports the runners and associated west commands listed below.

	flash	debug	rtt	debugserver	attach
openocd	✅ (default)	✅ (default)	✅	✅	✅
probe-rs	✅	✅	✅	✅

The KIT_PSE84_AI includes an onboard programmer/debugger (KitProg3) which can be used to program and debug both PSOC™ Edge E84 cores.

Board Setup

Connect a USB cable from your PC to the KitProg3 USB Type-C connector (J1). Open the KitProg3 serial port with a terminal of your choice (minicom, PuTTY, etc.) at 115200 8N1.

The examples below assume the default boot pin setting, which boots from external flash (see Secure Boot).

Infineon OpenOCD Installation

The ModusToolbox™ Programming Tools package includes Infineon OpenOCD. Alternatively, download the Infineon OpenOCD release for your system and extract it to a location of your choice.

Note

On Linux, KitProg3 needs device access rights. The ModusToolbox™ Programming Tools installer sets these up. For a standalone OpenOCD installation, run openocd/udev_rules/install_rules.sh.

Tell west where Infineon OpenOCD is installed. On Windows the executable is openocd.exe.

west config build.cmake-args -- "-DOPENOCD=path/to/infineon/openocd/bin/openocd"

Note

This replaces any existing build.cmake-args value. To set the path for a single command instead, use west flash --openocd <path>.

Building and Flashing

CM33:

# From the root of the zephyr repository
west build -b kit_pse84_ai/pse846gps2dbzc4a/m33 samples/hello_world
west flash

CM33 Non-Secure with TF-M:

# From the root of the zephyr repository
west build -b kit_pse84_ai/pse846gps2dbzc4a/m33/ns samples/hello_world
west flash

CM55 (sysbuild builds and flashes the enable_cm55 CM33 image as well):

# From the root of the zephyr repository
west build -b kit_pse84_ai/pse846gps2dbzc4a/m55 --sysbuild samples/hello_world
west flash

The console shows the board target that was built, for example:

*** Booting Zephyr OS build vX.Y.Z ***
Hello World! kit_pse84_ai/pse846gps2dbzc4a/m33

Use west flash --erase to erase the device before programming. This erases the user-programmable RRAM area and all external flash, including any stored settings. The extended boot, OEM policy and provisioned keys are not erased.

Debugging

CM33:

# From the root of the zephyr repository
west build -b kit_pse84_ai/pse846gps2dbzc4a/m33 samples/hello_world
west debug

For the CM55, west debug attaches to the CM55 on GDB port 3334.

Secure Boot

The PSOC™ Edge E84 MCU includes an Infineon extended boot stage, stored in a reserved RRAM region, that on reset jumps to the first application image. On the KIT_PSE84_AI the destination is selected by the level of the boot pin, which by default is pulled HIGH and causes the extended boot to jump to the first application located in external flash.

To make the extended boot jump to a first application located in internal RRAM, one of the following must be done:

Hardware rework: remove resistor R188 and populate resistor R187 to pull the boot pin LOW.
Reprovisioning (no hardware rework): reprovision the device using the same flow described in Enabling Secure Boot below, but customize the generated OEM policy JSON to ignore the boot pin state. While following the provisioning steps, after the OEM key pair has been generated, set oem_alt_boot to false in policy/policy_oem_provisioning.json in the project, before provisioning the kit.

In either case, the boot behavior is then locked to booting from RRAM and must be reverted (reattaching R188 / removing R187, or reprovisioning again with oem_alt_boot set back to true) to re-enable booting from external flash.

In all cases the first application image must be in MCUboot image format, i.e. it must be preceded by an MCUboot image header (magic number, header size, vector table address, image size) and followed by the trailer with the hash/signature TLVs. Out of the box, the device is not provisioned for secure boot, so the extended boot only checks the image format and hash; no cryptographic signature verification is performed against a provisioned key.

The MCUboot image format is produced automatically by the soc/infineon/edge/pse84/pse84_metadata.cmake helper pse84_add_extboot_metadata(), which invokes imgtool sign with the header address, header size and slot size derived from the devicetree memory map. By default this helper does not pass a signing key, which is sufficient for a non-provisioned device.

Enabling Secure Boot

To enable real signature verification by the extended boot, the device must be reprovisioned. Follow sections 2.2.1, 2.2.2 and 2.2.3 of the PSOC™ Edge Security Getting Started Application Note to:

Generate (or import) the OEM signing key pair.
Provision the device with the corresponding public key and lifecycle transition.
Program the desired security counter / anti-rollback value.

After the device has been reprovisioned, the pse84_add_extboot_metadata() function in soc/infineon/edge/pse84/pse84_metadata.cmake must be updated so that imgtool sign also receives the signing key and a security counter. The relevant additions are:

${PYTHON_EXECUTABLE} ${IMGTOOL} sign --version "0.0.0+0"
  --header-size ${header_size} --erased-val 0xff
  --slot-size ${slot_size} --hex-addr ${hex_addr}
  --key <oem-private-key-file>
  --security-counter <value>
  ${INPUT_FILE} ${OUTPUT_FILE}

Where <oem-private-key-file> is the path to the OEM private key file (e.g. a .pem file) matching the public key provisioned into the device, and <value> is the security counter assigned during provisioning. Without these additional parameters, images built for a provisioned device will be rejected by the extended boot.

TF-M Multicore Support

In this configuration TF-M runs on the CM33 Secure side and serves PSA requests from both the CM33 Non-Secure application and the CM55 application. The CM55 reaches TF-M through a mailbox-based relay. It is enabled with CONFIG_PSOC_EDGE_M55_SRF_SUPPORT, which must be set on both images.

Note

Unlike the standalone CM55 target, this configuration does not use sysbuild. The two images are built as separate Zephyr applications and flashed separately.

Building

The CM55 build uses PSA manifest headers generated by the CM33 Non-Secure (TF-M) build, so the CM33 image must be built first. The CM55 build is pointed at it with the PSE84_CM33_BUILD_DIR CMake variable, which must be the CM33 build directory (the one passed to west build -d). Use an absolute path.

Build the CM33 Non-Secure image:

west build -b kit_pse84_ai/pse846gps2dbzc4a/m33/ns \
           -d build_multicore_33 samples/hello_world \
           -- -DCONFIG_PSOC_EDGE_M55_SRF_SUPPORT=y

Build the CM55 image:

west build -b kit_pse84_ai/pse846gps2dbzc4a/m55 \
           -d build_multicore_55 samples/basic/blinky \
           -- -DCONFIG_PSOC_EDGE_M55_SRF_SUPPORT=y \
              -DPSE84_CM33_BUILD_DIR=<absolute-path-to>/build_multicore_33

If PSE84_CM33_BUILD_DIR is not given, it defaults to ${ZEPHYR_BASE}/build. If the directory does not contain tfm/generated/interface/include, the CM55 build stops with a FATAL_ERROR.

Flashing

Flash the CM55 image first. On reset the CM33 Non-Secure image starts the CM55, and it faults if no valid CM55 image is present.

west flash -d build_multicore_55
west flash -d build_multicore_33

PSOC™ Edge E84 AI Evaluation Kit

Overview

Boot Flow

Board Targets

Hardware

Kit Contents

Supported Features

kit_pse84_ai/pse846gps2dbzc4a/m33 target

kit_pse84_ai/pse846gps2dbzc4a/m33/ns target

kit_pse84_ai/pse846gps2dbzc4a/m55 target

Connections and IOs

Serial Port

System Clock

Programming and Debugging

Board Setup

Infineon OpenOCD Installation

Building and Flashing

Debugging

Secure Boot

Enabling Secure Boot

TF-M Multicore Support

Building

Flashing

References

`kit_pse84_ai/pse846gps2dbzc4a/m33` target

`kit_pse84_ai/pse846gps2dbzc4a/m33/ns` target

`kit_pse84_ai/pse846gps2dbzc4a/m55` target