ENE KB1200_EVB

Overview

The KB1200_EVB kit is a development platform to evaluate the ENE KB1200 series microcontrollers. This board needs to be mated with part number KB1200.

Hardware

  • ARM Cortex-M4F Processor

  • 512KB Flash and 320KB RAM

  • ADC & GPIO headers

  • SER1, SER2 and SER3

  • FAN PWM interface

  • ENE Debug interface

Supported Features

The kb1200_evb board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
kb1200_evb
/
kb1200

Type

Location

Description

Compatible

CPU

on-chip

ARM Cortex-M4 CPU1

arm,cortex-m4

ADC

on-chip

ENE KB1200 ADC controller1

ene,kb1200-adc

GPIO & Headers

on-chip

ENE KB1200 GPIO Port1 3

ene,kb1200-gpio

I2C

on-chip

ENE I2C/SMB controller2 8

ene,kb1200-i2c

Input

on-board

Group of GPIO-bound input keys1

gpio-keys

Interrupt controller

on-chip

ARMv7-M NVIC (Nested Vectored Interrupt Controller)1

arm,v7m-nvic

LED

on-board

Group of GPIO-controlled LEDs1

gpio-leds

Miscellaneous

on-chip

ENE, Power Manager1

ene,kb1200-pmu

on-chip

ENE, General Configuration1

ene,kb1200-gcfg

MTD

on-chip

Flash node1

soc-nv-flash

Pin control

on-chip

The ENE KB1200 pin controller is a singleton node responsible for controlling pin function selection and pin properties1

ene,kb1200-pinctrl

PWM

on-chip

ENE, Pulse Width Modulator (PWM) node4 8

ene,kb1200-pwm

Serial controller

on-chip

ENE KB1200 UART3

ene,kb1200-uart

SRAM

on-chip

Generic on-chip SRAM1

mmio-sram

Tachometer

on-chip

ENE KB1200 Tachometer4

ene,kb1200-tach

Timer

on-chip

ARMv7-M System Tick1

arm,armv7m-systick

Watchdog

on-chip

ENE watchdog timer1

ene,kb1200-watchdog

System Clock

The KB1200 MCU is configured to use the 96Mhz internal oscillator with the on-chip DPLL to generate a resulting EC clock rate of 96MHz/48MHz/24MHz/12MHz. See Processor clock control register (refer 5.1 General Configuration)

Programming and Debugging

The kb1200_evb board supports the runners and associated west commands listed below.

flash debug debugserver attach rtt
jlink
openocd ✅ (default) ✅ (default)

Flashing

If the correct headers are installed, this board supports SWD Debug Interface.

To flash with SWD, install the drivers for your programmer, for example: SEGGER J-link’s drivers are at https://www.segger.com/downloads/jlink/

Debugging

Use SWD with a J-Link

References