Zephyr API Documentation
4.0.99
A Scalable Open Source RTOS
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stm32wb_clock.h
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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_
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#include "
stm32_common_clocks.h
"
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#define STM32_CLOCK_BUS_AHB1 0x048
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#define STM32_CLOCK_BUS_AHB2 0x04c
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#define STM32_CLOCK_BUS_AHB3 0x050
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#define STM32_CLOCK_BUS_APB1 0x058
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#define STM32_CLOCK_BUS_APB1_2 0x05c
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#define STM32_CLOCK_BUS_APB2 0x060
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
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/* RM0434, ยง Clock configuration register (RCC_CCIPRx) */
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/* defined in stm32_common_clocks.h */
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/* Low speed clocks defined in stm32_common_clocks.h */
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#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
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#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
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#define STM32_SRC_HSE (STM32_SRC_MSI + 1)
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#define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
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#define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1)
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#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
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#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
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/* TODO: PLLSAI clocks */
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#define STM32_CLOCK_REG_MASK 0xFFU
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#define STM32_CLOCK_REG_SHIFT 0U
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#define STM32_CLOCK_SHIFT_MASK 0x1FU
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#define STM32_CLOCK_SHIFT_SHIFT 8U
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#define STM32_CLOCK_MASK_MASK 0x7U
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#define STM32_CLOCK_MASK_SHIFT 13U
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#define STM32_CLOCK_VAL_MASK 0x7U
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#define STM32_CLOCK_VAL_SHIFT 16U
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#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
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((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
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(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
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(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
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(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
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#define CCIPR_REG 0x88
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#define BDCR_REG 0x90
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#define CSR_REG 0x94
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#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
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#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
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#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
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#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
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#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
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#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
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#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
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#define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
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#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
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#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
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#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
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#define RFWKP_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CSR_REG)
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ */
stm32_common_clocks.h
zephyr
dt-bindings
clock
stm32wb_clock.h
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