Zephyr API Documentation 4.0.0-rc3
A Scalable Open Source RTOS
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stm32wb0_clock.h
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1/*
2 * Copyright (c) 2024 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
8
10#include "stm32_common_clocks.h"
11
17#define STM32_SRC_CLKSLOWMUX (STM32_SRC_LSI + 1)
18#define STM32_SRC_CLK16MHZ (STM32_SRC_CLKSLOWMUX + 1)
19#define STM32_SRC_CLK32MHZ (STM32_SRC_CLK16MHZ + 1)
20
22#define STM32_CLOCK_BUS_AHB0 0x50
23#define STM32_CLOCK_BUS_APB0 0x54
24#define STM32_CLOCK_BUS_APB1 0x58
25#define STM32_CLOCK_BUS_APB2 0x60
26
27#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB0
28#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
29
30#define STM32_CLOCK_REG_MASK (0xFFFFU)
31#define STM32_CLOCK_REG_SHIFT (0U)
32#define STM32_CLOCK_SHIFT_MASK (0x3FU)
33#define STM32_CLOCK_SHIFT_SHIFT (16U)
34#define STM32_CLOCK_MASK_MASK (0x1FU)
35#define STM32_CLOCK_MASK_SHIFT (22U)
36#define STM32_CLOCK_VAL_MASK STM32_CLOCK_MASK_MASK
37#define STM32_CLOCK_VAL_SHIFT (27U)
38
52#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
53 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
54 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
55 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
56 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
57
59#define CFGR_REG 0x08
60
62#define APB2ENR_REG 0x60
63
65#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 13, CFGR_REG) /* WB05/WB09 only */
66#define SPI2_I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 22, CFGR_REG) /* WB06/WB07 only */
67/* `mask` is only 0x1 for WB06/WB07, but a single definition with mask=0x3 is acceptable */
68#define SPI3_I2S3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CFGR_REG)
69
70#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ */