Zephyr API Documentation
4.0.0-rc3
A Scalable Open Source RTOS
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stm32wb0_clock.h
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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
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#include "
stm32_common_clocks.h
"
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#define STM32_SRC_CLKSLOWMUX (STM32_SRC_LSI + 1)
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#define STM32_SRC_CLK16MHZ (STM32_SRC_CLKSLOWMUX + 1)
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#define STM32_SRC_CLK32MHZ (STM32_SRC_CLK16MHZ + 1)
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#define STM32_CLOCK_BUS_AHB0 0x50
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#define STM32_CLOCK_BUS_APB0 0x54
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#define STM32_CLOCK_BUS_APB1 0x58
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#define STM32_CLOCK_BUS_APB2 0x60
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB0
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
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#define STM32_CLOCK_REG_MASK (0xFFFFU)
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#define STM32_CLOCK_REG_SHIFT (0U)
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#define STM32_CLOCK_SHIFT_MASK (0x3FU)
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#define STM32_CLOCK_SHIFT_SHIFT (16U)
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#define STM32_CLOCK_MASK_MASK (0x1FU)
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#define STM32_CLOCK_MASK_SHIFT (22U)
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#define STM32_CLOCK_VAL_MASK STM32_CLOCK_MASK_MASK
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#define STM32_CLOCK_VAL_SHIFT (27U)
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#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
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((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
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(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
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(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
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(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
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#define CFGR_REG 0x08
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#define APB2ENR_REG 0x60
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#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 13, CFGR_REG)
/* WB05/WB09 only */
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#define SPI2_I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 22, CFGR_REG)
/* WB06/WB07 only */
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/* `mask` is only 0x1 for WB06/WB07, but a single definition with mask=0x3 is acceptable */
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#define SPI3_I2S3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CFGR_REG)
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ */
stm32_common_clocks.h
zephyr
dt-bindings
clock
stm32wb0_clock.h
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