stm32wb0_clock.h

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/*
 * Copyright (c) 2024 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
 
#include "stm32_common_clocks.h"
 
#define STM32_SRC_CLKSLOWMUX            (STM32_SRC_LSI + 1)
#define STM32_SRC_CLK16MHZ              (STM32_SRC_CLKSLOWMUX + 1)
#define STM32_SRC_CLK32MHZ              (STM32_SRC_CLK16MHZ + 1)
 
#define STM32_CLOCK_BUS_AHB0    0x50
#define STM32_CLOCK_BUS_APB0    0x54
#define STM32_CLOCK_BUS_APB1    0x58
#define STM32_CLOCK_BUS_APB2    0x60
 
#define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_AHB0
#define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB2
 
#define STM32_CLOCK_REG_MASK    (0xFFFFU)
#define STM32_CLOCK_REG_SHIFT   (0U)
#define STM32_CLOCK_SHIFT_MASK  (0x3FU)
#define STM32_CLOCK_SHIFT_SHIFT (16U)
#define STM32_CLOCK_MASK_MASK   (0x1FU)
#define STM32_CLOCK_MASK_SHIFT  (22U)
#define STM32_CLOCK_VAL_MASK    STM32_CLOCK_MASK_MASK
#define STM32_CLOCK_VAL_SHIFT   (27U)
 
#define STM32_CLOCK(val, mask, shift, reg)                              \
        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |            \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |         \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
 
#define CFGR_REG        0x08
 
#define APB2ENR_REG     0x60
 
#define LPUART1_SEL(val)        STM32_CLOCK(val, 1, 13, CFGR_REG)       /* WB05/WB09 only */
#define SPI2_I2S2_SEL(val)      STM32_CLOCK(val, 1, 22, CFGR_REG)       /* WB06/WB07 only */
/* `mask` is only 0x1 for WB06/WB07, but a single definition with mask=0x3 is acceptable */
#define SPI3_I2S3_SEL(val)      STM32_CLOCK(val, 3, 22, CFGR_REG)
 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ */