Zephyr API Documentation
4.1.99
A Scalable Open Source RTOS
4.1.99
Toggle main menu visibility
Main Page
Related Pages
Topics
Data Structures
Data Structures
Data Structure Index
Data Fields
All
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
Functions
Variables
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
Enumerations
Enumerator
Files
File List
Globals
All
$
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
Functions
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
Variables
$
a
b
c
d
f
g
h
i
k
l
m
n
o
p
r
s
t
u
x
z
Typedefs
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
Enumerations
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
r
s
t
u
v
w
x
z
Enumerator
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
r
s
t
u
v
w
x
z
Macros
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
•
All
Data Structures
Files
Functions
Variables
Typedefs
Enumerations
Enumerator
Macros
Modules
Pages
Loading...
Searching...
No Matches
stm32n6_clock.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2024 STMicroelectronics
3
*
4
* SPDX-License-Identifier: Apache-2.0
5
*/
6
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_
7
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_
8
9
#include "
stm32_common_clocks.h
"
10
13
/* RM0486, Figures 37 and 45 on clock distribution description */
14
16
/* defined in stm32_common_clocks.h */
18
#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
19
#define STM32_SRC_HSI (STM32_SRC_HSE + 1)
20
#define STM32_SRC_MSI (STM32_SRC_HSI + 1)
22
#define STM32_SRC_PLL1 (STM32_SRC_MSI + 1)
23
#define STM32_SRC_PLL2 (STM32_SRC_PLL1 + 1)
24
#define STM32_SRC_PLL3 (STM32_SRC_PLL2 + 1)
25
#define STM32_SRC_PLL4 (STM32_SRC_PLL3 + 1)
27
#define STM32_SRC_CKPER (STM32_SRC_PLL4 + 1)
28
#define STM32_SRC_IC1 (STM32_SRC_CKPER + 1)
29
#define STM32_SRC_IC2 (STM32_SRC_IC1 + 1)
30
#define STM32_SRC_IC3 (STM32_SRC_IC2 + 1)
31
#define STM32_SRC_IC4 (STM32_SRC_IC3 + 1)
32
#define STM32_SRC_IC5 (STM32_SRC_IC4 + 1)
33
#define STM32_SRC_IC6 (STM32_SRC_IC5 + 1)
34
#define STM32_SRC_IC7 (STM32_SRC_IC6 + 1)
35
#define STM32_SRC_IC8 (STM32_SRC_IC7 + 1)
36
#define STM32_SRC_IC9 (STM32_SRC_IC8 + 1)
37
#define STM32_SRC_IC10 (STM32_SRC_IC9 + 1)
38
#define STM32_SRC_IC11 (STM32_SRC_IC10 + 1)
39
#define STM32_SRC_IC12 (STM32_SRC_IC11 + 1)
40
#define STM32_SRC_IC13 (STM32_SRC_IC12 + 1)
41
#define STM32_SRC_IC14 (STM32_SRC_IC13 + 1)
42
#define STM32_SRC_IC15 (STM32_SRC_IC14 + 1)
43
#define STM32_SRC_IC16 (STM32_SRC_IC15 + 1)
44
#define STM32_SRC_IC17 (STM32_SRC_IC16 + 1)
45
#define STM32_SRC_IC18 (STM32_SRC_IC17 + 1)
46
#define STM32_SRC_IC19 (STM32_SRC_IC18 + 1)
47
#define STM32_SRC_IC20 (STM32_SRC_IC19 + 1)
48
#define STM32_SRC_HSI_DIV (STM32_SRC_IC20 + 1)
49
#define STM32_SRC_TIMG (STM32_SRC_HSI_DIV + 1)
50
#define STM32_SRC_HCLK1 (STM32_SRC_TIMG + 1)
51
#define STM32_SRC_HCLK2 (STM32_SRC_HCLK1 + 1)
52
#define STM32_SRC_HCLK3 (STM32_SRC_HCLK2 + 1)
53
#define STM32_SRC_HCLK4 (STM32_SRC_HCLK3 + 1)
54
#define STM32_SRC_HCLK5 (STM32_SRC_HCLK4 + 1)
55
#define STM32_SRC_PCLK1 (STM32_SRC_HCLK5 + 1)
56
#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)
57
#define STM32_SRC_PCLK4 (STM32_SRC_PCLK2 + 1)
58
#define STM32_SRC_PCLK5 (STM32_SRC_PCLK4 + 1)
59
61
/* #define STM32_SRC_I2SCKIN TBD */
62
64
#define STM32_CLOCK_BUS_AHB1 0x250
65
#define STM32_CLOCK_BUS_AHB2 0x254
66
#define STM32_CLOCK_BUS_AHB3 0x258
67
#define STM32_CLOCK_BUS_AHB4 0x25C
68
#define STM32_CLOCK_BUS_AHB5 0x260
69
#define STM32_CLOCK_BUS_APB1 0x264
70
#define STM32_CLOCK_BUS_APB1_2 0x268
71
#define STM32_CLOCK_BUS_APB2 0x26C
72
#define STM32_CLOCK_BUS_APB3 0x270
73
#define STM32_CLOCK_BUS_APB4 0x274
74
#define STM32_CLOCK_BUS_APB4_2 0x278
75
#define STM32_CLOCK_BUS_APB5 0x27C
76
77
#define STM32_CLOCK_LP_BUS_SHIFT 0x40
78
79
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
80
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB5
81
83
#define CCIPR1_REG 0x144
84
#define CCIPR2_REG 0x148
85
#define CCIPR3_REG 0x14C
86
#define CCIPR4_REG 0x150
87
#define CCIPR5_REG 0x154
88
#define CCIPR6_REG 0x158
89
#define CCIPR7_REG 0x15C
90
#define CCIPR8_REG 0x160
91
#define CCIPR9_REG 0x164
92
#define CCIPR12_REG 0x170
93
#define CCIPR13_REG 0x174
94
#define CCIPR14_REG 0x178
95
98
#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR1_REG)
99
#define ADC12_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR1_REG)
100
#define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG)
102
#define ETH1PTP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
103
#define ETH1CLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
104
#define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR2_REG)
105
#define ETH1REFCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR2_REG)
106
#define ETH1GTXCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR2_REG)
108
#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)
109
#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR3_REG)
111
#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR4_REG)
112
#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR4_REG)
113
#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR4_REG)
114
#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR4_REG)
115
#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR4_REG)
116
#define I3C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR4_REG)
117
#define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR4_REG)
119
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR5_REG)
120
#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR5_REG)
121
#define MDF1SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR5_REG)
123
#define XSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR6_REG)
124
#define XSPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR6_REG)
125
#define XSPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR6_REG)
126
#define OTGPHY1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR6_REG)
127
#define OTGPHY1CKREF_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR6_REG)
128
#define OTGPHY2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR6_REG)
129
#define OTGPHY2CKREF_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR6_REG)
131
#define PER_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR7_REG)
132
#define PSSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR7_REG)
133
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR7_REG)
134
#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR7_REG)
135
#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR7_REG)
137
#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR8_REG)
138
#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR8_REG)
140
#define SPDIFRX1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR9_REG)
141
#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR9_REG)
142
#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR9_REG)
143
#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR9_REG)
144
#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR9_REG)
145
#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR9_REG)
146
#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR9_REG)
148
#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR12_REG)
149
#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR12_REG)
150
#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR12_REG)
151
#define LPTIM4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR12_REG)
152
#define LPTIM5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR12_REG)
154
#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR13_REG)
155
#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR13_REG)
156
#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR13_REG)
157
#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR13_REG)
158
#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR13_REG)
159
#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR13_REG)
160
#define UART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR13_REG)
161
#define UART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, CCIPR13_REG)
163
#define UART9_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR14_REG)
164
#define USART10_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR14_REG)
165
#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR14_REG)
166
168
#define ICxCFGR_REG(ic) (0xC4 + ((ic) - 1) * 4)
169
171
#define ICx_PLLy_SEL(ic, pll) STM32_DT_CLOCK_SELECT((pll) - 1, 3, 28, ICxCFGR_REG(ic))
172
174
#define CFGR1_REG 0x20
175
177
#define CPU_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR1_REG)
178
179
#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_ */
stm32_common_clocks.h
zephyr
dt-bindings
clock
stm32n6_clock.h
Generated on Fri May 16 2025 18:06:43 for Zephyr API Documentation by
1.12.0
1.12.0 