Zephyr API Documentation 4.0.0-rc3
A Scalable Open Source RTOS
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stm32h7_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
8
10
13/* RM0468, Table 56 Kernel clock dictribution summary */
14
16/* defined in stm32_common_clocks.h */
17
19/* Low speed clocks defined in stm32_common_clocks.h */
20#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
21#define STM32_SRC_HSI48 (STM32_SRC_HSE + 1)
22#define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1) /* HSI + HSIKERON */
23#define STM32_SRC_CSI_KER (STM32_SRC_HSI_KER + 1) /* CSI + CSIKERON */
25#define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1)
26#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
27#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
28#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
29#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
30#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
31#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
32#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
33#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
35#define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1)
37/* #define STM32_SRC_I2SCKIN TBD */
38/* #define STM32_SRC_SPDIFRX TBD */
39
40
42#define STM32_CLOCK_BUS_AHB3 0x0D4
43#define STM32_CLOCK_BUS_AHB1 0x0D8
44#define STM32_CLOCK_BUS_AHB2 0x0DC
45#define STM32_CLOCK_BUS_AHB4 0x0E0
46#define STM32_CLOCK_BUS_APB3 0x0E4
47#define STM32_CLOCK_BUS_APB1 0x0E8
48#define STM32_CLOCK_BUS_APB1_2 0x0EC
49#define STM32_CLOCK_BUS_APB2 0x0F0
50#define STM32_CLOCK_BUS_APB4 0x0F4
51 /* TBD: To remove ? */
52#define STM32_SRC_PCLK1 STM32_CLOCK_BUS_APB1
53#define STM32_SRC_PCLK2 STM32_CLOCK_BUS_APB2
54#define STM32_SRC_HCLK3 STM32_CLOCK_BUS_AHB3
55#define STM32_SRC_PCLK3 STM32_CLOCK_BUS_APB3
56#define STM32_SRC_PCLK4 STM32_CLOCK_BUS_APB4
57
58#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB3
59#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB4
60
61#define STM32_CLOCK_REG_MASK 0xFFU
62#define STM32_CLOCK_REG_SHIFT 0U
63#define STM32_CLOCK_SHIFT_MASK 0x1FU
64#define STM32_CLOCK_SHIFT_SHIFT 8U
65#define STM32_CLOCK_MASK_MASK 0x7U
66#define STM32_CLOCK_MASK_SHIFT 13U
67#define STM32_CLOCK_VAL_MASK 0x7U
68#define STM32_CLOCK_VAL_SHIFT 16U
69
83#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
84 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
85 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
86 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
87 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
88
90#define D1CCIPR_REG 0x4C
91#define D2CCIP1R_REG 0x50
92#define D2CCIP2R_REG 0x54
93#define D3CCIPR_REG 0x58
94
96#define BDCR_REG 0x70
97
99#define CFGR_REG 0x10
100
103#define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG)
104#define QSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
105#define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, D1CCIPR_REG)
106#define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 16, D1CCIPR_REG)
107#define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG)
108/* Device domain clocks selection helpers (RM0468.pdf) */
109#define OSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
111#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP1R_REG)
112#define SAI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, D2CCIP1R_REG)
113#define SPI123_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, D2CCIP1R_REG)
114#define SPI45_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIP1R_REG)
115#define SPDIF_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP1R_REG)
116#define DFSDM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, D2CCIP1R_REG)
117#define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D2CCIP1R_REG)
118#define SWP_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, D2CCIP1R_REG)
120#define USART2345678_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP2R_REG)
121#define USART16_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, D2CCIP2R_REG)
122#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIP2R_REG)
123#define I2C123_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIP2R_REG)
124#define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP2R_REG)
125#define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, D2CCIP2R_REG)
126#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D2CCIP2R_REG)
128#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG)
129#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D3CCIPR_REG)
130#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 10, D3CCIPR_REG)
131#define LPTIM345_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 13, D3CCIPR_REG)
132#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, D3CCIPR_REG)
133#define SAI4A_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 21, D3CCIPR_REG)
134#define SAI4B_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, D3CCIPR_REG)
135#define SPI6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D3CCIPR_REG)
137#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
139#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 22, CFGR_REG)
140#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 18, CFGR_REG)
141#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0xF, 29, CFGR_REG)
142#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 25, CFGR_REG)
143
144#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */