Zephyr API Documentation
4.0.99
A Scalable Open Source RTOS
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stm32f7_clock.h
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/*
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* Copyright (c) 2022 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_
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#include "
stm32_common_clocks.h
"
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#define STM32_CLOCK_BUS_AHB1 0x030
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#define STM32_CLOCK_BUS_AHB2 0x034
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#define STM32_CLOCK_BUS_AHB3 0x038
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#define STM32_CLOCK_BUS_APB1 0x040
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#define STM32_CLOCK_BUS_APB2 0x044
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#define STM32_CLOCK_BUS_APB3 0x0A8
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
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/* RM0386, 0390, 0402, 0430 ยง Dedicated Clock configuration register (RCC_DCKCFGRx) */
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/* defined in stm32_common_clocks.h */
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/* Low speed clocks defined in stm32_common_clocks.h */
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#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSE (STM32_SRC_HSI + 1)
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#define STM32_SRC_PLL_P (STM32_SRC_HSE + 1)
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#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
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#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
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#define STM32_SRC_PCLK (STM32_SRC_PLL_R + 1)
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#define STM32_SRC_PLLI2S_R (STM32_SRC_PCLK + 1)
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#define STM32_CLOCK_REG_MASK 0xFFU
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#define STM32_CLOCK_REG_SHIFT 0U
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#define STM32_CLOCK_SHIFT_MASK 0x1FU
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#define STM32_CLOCK_SHIFT_SHIFT 8U
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#define STM32_CLOCK_MASK_MASK 0x7U
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#define STM32_CLOCK_MASK_SHIFT 13U
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#define STM32_CLOCK_VAL_MASK 0x7U
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#define STM32_CLOCK_VAL_SHIFT 16U
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#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
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((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
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(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
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(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
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(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
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#define CFGR_REG 0x08
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#define BDCR_REG 0x70
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#define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
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#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG)
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#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
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#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)
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#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)
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#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
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#define DCKCFGR1_REG 0x8C
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#define DCKCFGR2_REG 0x90
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#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, DCKCFGR2_REG)
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#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, DCKCFGR2_REG)
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#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, DCKCFGR2_REG)
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#define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, DCKCFGR2_REG)
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#define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, DCKCFGR2_REG)
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#define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, DCKCFGR2_REG)
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#define USART7_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, DCKCFGR2_REG)
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#define USART8_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, DCKCFGR2_REG)
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#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, DCKCFGR2_REG)
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#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, DCKCFGR2_REG)
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#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR2_REG)
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#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)
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#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, DCKCFGR2_REG)
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#define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 26, DCKCFGR2_REG)
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#define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)
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#define SDMMC1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)
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#define SDMMC2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR2_REG)
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#define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 30, DCKCFGR2_REG)
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ */
stm32_common_clocks.h
zephyr
dt-bindings
clock
stm32f7_clock.h
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