Zephyr API Documentation
4.0.99
A Scalable Open Source RTOS
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stm32f3_clock.h
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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
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#include "
stm32_common_clocks.h
"
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#define STM32_CLOCK_BUS_AHB1 0x014
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#define STM32_CLOCK_BUS_APB2 0x018
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#define STM32_CLOCK_BUS_APB1 0x01c
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
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/* RM0316, ยง9.4.13 Clock configuration register (RCC_CFGR3) */
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/* Defined in stm32_common_clocks.h */
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/* Low speed clocks defined in stm32_common_clocks.h */
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#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
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/* #define STM32_SRC_HSI48 TDB */
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#define STM32_SRC_PCLK (STM32_SRC_HSI + 1)
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#define STM32_SRC_PLLCLK (STM32_SRC_PCLK + 1)
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#define STM32_CLOCK_REG_MASK 0xFFU
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#define STM32_CLOCK_REG_SHIFT 0U
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#define STM32_CLOCK_SHIFT_MASK 0x1FU
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#define STM32_CLOCK_SHIFT_SHIFT 8U
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#define STM32_CLOCK_MASK_MASK 0x7U
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#define STM32_CLOCK_MASK_SHIFT 13U
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#define STM32_CLOCK_VAL_MASK 0x7U
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#define STM32_CLOCK_VAL_SHIFT 16U
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#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
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((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
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(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
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(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
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(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
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#define CFGR_REG 0x04
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#define CFGR3_REG 0x30
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#define BDCR_REG 0x20
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#define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
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#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
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#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG)
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#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)
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#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)
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#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG)
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#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)
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#define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG)
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#define TIM8_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 9, CFGR3_REG)
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#define TIM15_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 10, CFGR3_REG)
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#define TIM16_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 11, CFGR3_REG)
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#define TIM17_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 13, CFGR3_REG)
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#define TIM20_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, CFGR3_REG)
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#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)
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#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)
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#define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CFGR3_REG)
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#define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CFGR3_REG)
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#define TIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, CFGR3_REG)
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#define TIM3_4_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 25, CFGR3_REG)
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#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */
stm32_common_clocks.h
zephyr
dt-bindings
clock
stm32f3_clock.h
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