doxygen/html/sf32lb__reset_8h_source.html

/*

 * Copyright (c) 2025 Qingsong Gou <gouqs@hotmail.com>

 * SPDX-License-Identifier: Apache-2.0

 */


#ifndef _ZEPHYR_INCLUDE_DT_BINDINGS_RESET_SF32LB_RESET_H_

#define _ZEPHYR_INCLUDE_DT_BINDINGS_RESET_SF32LB_RESET_H_


#define SF32LB_RESET_DMAC1          (0U)

#define SF32LB_RESET_MAILBOX1       (1U)

#define SF32LB_RESET_PINMUX1        (2U)

#define SF32LB_RESET_USART1         (3U)

#define SF32LB_RESET_USART2         (4U)

#define SF32LB_RESET_EZIP           (5U)

#define SF32LB_RESET_EPIC           (6U)

#define SF32LB_RESET_LCDC1          (7U)

#define SF32LB_RESET_I2S1           (8U)

#define SF32LB_RESET_SYSCFG1        (10U)

#define SF32LB_RESET_EFUSEC         (11U)

#define SF32LB_RESET_AES            (12U)

#define SF32LB_RESET_CRC1           (13U)

#define SF32LB_RESET_TRNG           (14U)

#define SF32LB_RESET_GPTIM1         (15U)

#define SF32LB_RESET_GPTIM2         (16U)

#define SF32LB_RESET_BTIM1          (17U)

#define SF32LB_RESET_BTIM2          (18U)

#define SF32LB_RESET_SPI1           (20U)

#define SF32LB_RESET_SPI2           (21U)

#define SF32LB_RESET_EXTDMA         (22U)

#define SF32LB_RESET_PDM1           (25U)

#define SF32LB_RESET_I2C1           (27U)

#define SF32LB_RESET_I2C2           (28U)

#define SF32LB_RESET_PTC1           (31U)


#define SF32LB_RESET_GPIO1          (32U)

#define SF32LB_RESET_MPI1           (33U)

#define SF32LB_RESET_MPI2           (34U)

#define SF32LB_RESET_SDMMC1         (36U)

#define SF32LB_RESET_USBC           (38U)

#define SF32LB_RESET_I2C3           (40U)

#define SF32LB_RESET_ATIM1          (41U)

#define SF32LB_RESET_USART3         (44U)

#define SF32LB_RESET_AUDCODEC       (51U)

#define SF32LB_RESET_AUDPRC         (52U)

#define SF32LB_RESET_GPADC          (54U)

#define SF32LB_RESET_TSEN           (55U)

#define SF32LB_RESET_I2C4           (57U)


#endif /* _ZEPHYR_INCLUDE_DT_BINDINGS_RESET_SF32LB_RESET_H_ */