Zephyr API Documentation 4.0.0-rc2
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
gd32f3x0.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2022 Teslabs Engineering S.L.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F3X0_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F3X0_H_
9
10#include "gd32-common.h"
11
17#define GD32_APB2RST_OFFSET 0x0CU
18#define GD32_APB1RST_OFFSET 0x10U
19#define GD32_AHBRST_OFFSET 0x28U
20#define GD32_ADDAPB1RST_OFFSET 0xFCU
21
29/* APB2 peripherals */
30#define GD32_RESET_CFGCMP GD32_RESET_CONFIG(APB2RST, 0U)
31#define GD32_RESET_ADC GD32_RESET_CONFIG(APB2RST, 9U)
32#define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U)
33#define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U)
34#define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U)
35#define GD32_RESET_TIMER14 GD32_RESET_CONFIG(APB2RST, 16U)
36#define GD32_RESET_TIMER15 GD32_RESET_CONFIG(APB2RST, 17U)
37#define GD32_RESET_TIMER16 GD32_RESET_CONFIG(APB2RST, 18U)
38
39/* APB1 peripherals */
40#define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U)
41#define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U)
42#define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U)
43#define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U)
44#define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U)
45#define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U)
46#define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
47#define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U)
48#define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U)
49#define GD32_RESET_CEC GD32_RESET_CONFIG(APB1RST, 30U)
50
51/* AHB peripherals */
52#define GD32_RESET_USBFS GD32_RESET_CONFIG(AHBRST, 12U)
53#define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHBRST, 17U)
54#define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHBRST, 18U)
55#define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHBRST, 19U)
56#define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHBRST, 20U)
57#define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHBRST, 22U)
58#define GD32_RESET_TSI GD32_RESET_CONFIG(AHBRST, 24U)
59
60/* APB1 additional peripherals */
61#define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U)
62
65#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F3X0_H_ */