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Zephyr API Documentation 4.4.99
A Scalable Open Source RTOS
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TI MSPM0 UART FIFO threshold level definitions. More...
Go to the source code of this file.
Macros | |
MSPM0 UART RX FIFO threshold levels | |
| #define | MSPM0_UART_RX_FIFO_LEVEL_ONE_ENTRY 0 |
| At least one entry is present. | |
| #define | MSPM0_UART_RX_FIFO_LEVEL_1_4_FULL 1 |
| RX FIFO is 1/4 full. | |
| #define | MSPM0_UART_RX_FIFO_LEVEL_1_2_FULL 2 |
| RX FIFO is 1/2 full. | |
| #define | MSPM0_UART_RX_FIFO_LEVEL_3_4_FULL 3 |
| RX FIFO is 3/4 full. | |
| #define | MSPM0_UART_RX_FIFO_LEVEL_FULL 4 |
| RX FIFO is full. | |
MSPM0 UART TX FIFO threshold levels | |
| #define | MSPM0_UART_TX_FIFO_LEVEL_ONE_ENTRY 0 |
| TX FIFO has at least one entry available. | |
| #define | MSPM0_UART_TX_FIFO_LEVEL_1_4_EMPTY 1 |
| TX FIFO is 1/4 empty. | |
| #define | MSPM0_UART_TX_FIFO_LEVEL_1_2_EMPTY 2 |
| TX FIFO is 1/2 empty. | |
| #define | MSPM0_UART_TX_FIFO_LEVEL_3_4_EMPTY 3 |
| TX FIFO is 3/4 empty. | |
| #define | MSPM0_UART_TX_FIFO_LEVEL_EMPTY 4 |
| TX FIFO is empty. | |
TI MSPM0 UART FIFO threshold level definitions.
| #define MSPM0_UART_RX_FIFO_LEVEL_1_2_FULL 2 |
RX FIFO is 1/2 full.
| #define MSPM0_UART_RX_FIFO_LEVEL_1_4_FULL 1 |
RX FIFO is 1/4 full.
| #define MSPM0_UART_RX_FIFO_LEVEL_3_4_FULL 3 |
RX FIFO is 3/4 full.
| #define MSPM0_UART_RX_FIFO_LEVEL_FULL 4 |
RX FIFO is full.
| #define MSPM0_UART_RX_FIFO_LEVEL_ONE_ENTRY 0 |
At least one entry is present.
| #define MSPM0_UART_TX_FIFO_LEVEL_1_2_EMPTY 2 |
TX FIFO is 1/2 empty.
| #define MSPM0_UART_TX_FIFO_LEVEL_1_4_EMPTY 1 |
TX FIFO is 1/4 empty.
| #define MSPM0_UART_TX_FIFO_LEVEL_3_4_EMPTY 3 |
TX FIFO is 3/4 empty.
| #define MSPM0_UART_TX_FIFO_LEVEL_EMPTY 4 |
TX FIFO is empty.
| #define MSPM0_UART_TX_FIFO_LEVEL_ONE_ENTRY 0 |
TX FIFO has at least one entry available.