Zephyr API Documentation 4.0.0-rc2
A Scalable Open Source RTOS
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Macros | |
#define | DT_MEM_XTENSA_MASK DT_MEM_ARCH_ATTR_MASK |
#define | DT_MEM_XTENSA_GET(x) |
#define | DT_MEM_XTENSA(x) |
#define | ATTR_XTENSA_INSTR_ROM BIT(0) |
#define | ATTR_XTENSA_INSTR_RAM BIT(1) |
#define | ATTR_XTENSA_DATA_ROM BIT(2) |
#define | ATTR_XTENSA_DATA_RAM BIT(3) |
#define | ATTR_XTENSA_XLMI BIT(4) |
#define | DT_MEM_XTENSA_INSTR_ROM DT_MEM_XTENSA(ATTR_XTENSA_INSTR_ROM) |
#define | DT_MEM_XTENSA_INSTR_RAM DT_MEM_XTENSA(ATTR_XTENSA_INSTR_RAM) |
#define | DT_MEM_XTENSA_DATA_ROM DT_MEM_XTENSA(ATTR_XTENSA_DATA_ROM) |
#define | DT_MEM_XTENSA_DATA_RAM DT_MEM_XTENSA(ATTR_XTENSA_DATA_RAM) |
#define | DT_MEM_XTENSA_XLMI DT_MEM_XTENSA(ATTR_XTENSA_XLMI) |
#define | DT_MEM_XTENSA_UNKNOWN DT_MEM_ARCH_ATTR_UNKNOWN |
#define ATTR_XTENSA_DATA_RAM BIT(3) |
#define ATTR_XTENSA_DATA_ROM BIT(2) |
#define ATTR_XTENSA_INSTR_RAM BIT(1) |
#define ATTR_XTENSA_INSTR_ROM BIT(0) |
#define ATTR_XTENSA_XLMI BIT(4) |
#define DT_MEM_XTENSA | ( | x | ) |
#define DT_MEM_XTENSA_DATA_RAM DT_MEM_XTENSA(ATTR_XTENSA_DATA_RAM) |
#define DT_MEM_XTENSA_DATA_ROM DT_MEM_XTENSA(ATTR_XTENSA_DATA_ROM) |
#define DT_MEM_XTENSA_GET | ( | x | ) |
#define DT_MEM_XTENSA_INSTR_RAM DT_MEM_XTENSA(ATTR_XTENSA_INSTR_RAM) |
#define DT_MEM_XTENSA_INSTR_ROM DT_MEM_XTENSA(ATTR_XTENSA_INSTR_ROM) |
#define DT_MEM_XTENSA_MASK DT_MEM_ARCH_ATTR_MASK |
#define DT_MEM_XTENSA_UNKNOWN DT_MEM_ARCH_ATTR_UNKNOWN |
#define DT_MEM_XTENSA_XLMI DT_MEM_XTENSA(ATTR_XTENSA_XLMI) |