BCM283x interrupt controllers

Macros
#define	BCM283X_ARMC_IRQ_BASE   32U
	First Zephyr IRQ number routed to the BCM2835 ARMC peripheral aggregator.
#define	BCM283X_ARMC_IRQ_LIMIT   (BCM283X_ARMC_IRQ_BASE + 96U)
	One past the last ARMC IRQ in the Zephyr IRQ space.
#define	BCM283X_IRQ_IS_L1(irq)
	True when irq falls in the BCM2836 ARM-local intc range (0..9).
#define	BCM283X_IRQ_IS_ARMC(irq)
	True when irq falls in the BCM2835 ARMC peripheral range (32..127).
#define	BCM2836_L1_IRQ_GPU_BIT   8U
	L1 IRQ_SOURCE bit position for the GPU cascade.
#define	BCM2836_L1_IRQ_PMU_BIT   9U
	L1 IRQ_SOURCE bit position for the per-core PMU IRQ.

Functions
void	bcm2836_l1_intc_init (void)
	Initialise the BCM2836 ARM-local interrupt controller.
void	bcm2836_l1_intc_irq_enable (unsigned int irq)
	Enable an L1 IRQ source.
void	bcm2836_l1_intc_irq_disable (unsigned int irq)
	Disable an L1 IRQ source.
int	bcm2836_l1_intc_irq_is_enabled (unsigned int irq)
	Query whether an L1 IRQ source is currently enabled.
unsigned int	bcm2836_l1_intc_irq_get_active (void)
	Decode the firing L1 IRQ.
void	bcm2835_armctrl_ic_init (void)
	Initialise the BCM2835 ARMC peripheral interrupt controller.
void	bcm2835_armctrl_ic_irq_enable (unsigned int irq)
	Enable an ARMC peripheral IRQ source.
void	bcm2835_armctrl_ic_irq_disable (unsigned int irq)
	Disable an ARMC peripheral IRQ source.
int	bcm2835_armctrl_ic_irq_is_enabled (unsigned int irq)
	Query whether an ARMC peripheral IRQ source is enabled.
unsigned int	bcm2835_armctrl_ic_irq_get_active (void)
	Decode the firing ARMC peripheral IRQ.

Detailed Description

Macro Definition Documentation

BCM2836_L1_IRQ_GPU_BIT

#define BCM2836_L1_IRQ_GPU_BIT   8U

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

L1 IRQ_SOURCE bit position for the GPU cascade.

Also used as the Zephyr IRQ number for the cascade entry. ISRs are never registered at this index; when the L1 intc reports it, the SoC dispatcher transparently walks down into the ARMC controller to find the actual peripheral IRQ.

BCM2836_L1_IRQ_PMU_BIT

#define BCM2836_L1_IRQ_PMU_BIT   9U

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

L1 IRQ_SOURCE bit position for the per-core PMU IRQ.

Also the Zephyr IRQ number for the PMU.

BCM283X_ARMC_IRQ_BASE

#define BCM283X_ARMC_IRQ_BASE   32U

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

First Zephyr IRQ number routed to the BCM2835 ARMC peripheral aggregator.

BCM283X_ARMC_IRQ_LIMIT

#define BCM283X_ARMC_IRQ_LIMIT   (BCM283X_ARMC_IRQ_BASE + 96U)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

One past the last ARMC IRQ in the Zephyr IRQ space.

BCM283X_IRQ_IS_ARMC

#define BCM283X_IRQ_IS_ARMC

(

irq

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Value:

((irq) >= BCM283X_ARMC_IRQ_BASE && \
(irq) < BCM283X_ARMC_IRQ_LIMIT)

True when irq falls in the BCM2835 ARMC peripheral range (32..127).

BCM283X_IRQ_IS_L1

#define BCM283X_IRQ_IS_L1

(

irq

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Value:

((irq) < BCM283X_ARMC_IRQ_BASE)

True when irq falls in the BCM2836 ARM-local intc range (0..9).

Function Documentation

bcm2835_armctrl_ic_init()

void bcm2835_armctrl_ic_init

(

void

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Initialise the BCM2835 ARMC peripheral interrupt controller.

Maps the MMIO bank via device_map() and disables every bank-0, PEND1 and PEND2 source. Invoked by the SoC's z_soc_irq_init() during arch boot, before any SYS_INIT priority.

bcm2835_armctrl_ic_irq_disable()

void bcm2835_armctrl_ic_irq_disable

(

unsigned int

irq

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Disable an ARMC peripheral IRQ source.

Parameters

irq	Zephyr IRQ number in the ARMC range. Out-of-range callers are silently ignored.

bcm2835_armctrl_ic_irq_enable()

void bcm2835_armctrl_ic_irq_enable

(

unsigned int

irq

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Enable an ARMC peripheral IRQ source.

Parameters

irq	Zephyr IRQ number in the ARMC range (BCM283X_ARMC_IRQ_BASE .. BCM283X_ARMC_IRQ_LIMIT - 1). Calls outside the range are silently ignored.

bcm2835_armctrl_ic_irq_get_active()

unsigned int bcm2835_armctrl_ic_irq_get_active

(

void

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Decode the firing ARMC peripheral IRQ.

Encapsulates the bank-0 shortcut-bit decode (Quirk 1 in the BCM2835 ARM Peripherals datasheet ch. 7) and falls through to the PEND1 / PEND2 walk only when no shortcut bit is set.

Returns

The Zephyr IRQ number of the firing peripheral, or CONFIG_NUM_IRQS if no ARMC source is asserted.

bcm2835_armctrl_ic_irq_is_enabled()

int bcm2835_armctrl_ic_irq_is_enabled

(

unsigned int

irq

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Query whether an ARMC peripheral IRQ source is enabled.

Parameters

irq	Zephyr IRQ number in the ARMC range.

Return values

1	if enabled.
0	if disabled, or irq is outside the ARMC range.

bcm2836_l1_intc_init()

void bcm2836_l1_intc_init

(

void

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Initialise the BCM2836 ARM-local interrupt controller.

Maps the MMIO bank via device_map() and masks all locally-routed sources for core 0. Invoked by the SoC's z_soc_irq_init() during arch boot, before any SYS_INIT priority.

bcm2836_l1_intc_irq_disable()

void bcm2836_l1_intc_irq_disable

(

unsigned int

irq

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Disable an L1 IRQ source.

Parameters

irq	Zephyr IRQ number in the L1 range (0..9).

bcm2836_l1_intc_irq_enable()

void bcm2836_l1_intc_irq_enable

(

unsigned int

irq

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Enable an L1 IRQ source.

Parameters

irq	Zephyr IRQ number in the L1 range (0..9). IRQ 8 (GPU cascade) is implicit and has no per-IRQ enable bit.

bcm2836_l1_intc_irq_get_active()

unsigned int bcm2836_l1_intc_irq_get_active

(

void

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Decode the firing L1 IRQ.

Returns

The Zephyr IRQ number of the firing source, or CONFIG_NUM_IRQS if no L1 source is asserted. When the GPU cascade bit fires the caller is expected to walk into bcm2835_armctrl_ic_irq_get_active() next.

bcm2836_l1_intc_irq_is_enabled()

int bcm2836_l1_intc_irq_is_enabled

(

unsigned int

irq

)

#include <zephyr/drivers/interrupt_controller/intc_bcm283x.h>

Query whether an L1 IRQ source is currently enabled.

Parameters

irq	Zephyr IRQ number in the L1 range.

Return values

1	if enabled.
0	if disabled, or for PMU (no readback path).