esp-pinctrl-common.h File Reference

#include <zephyr/dt-bindings/dt-util.h>

Go to the source code of this file.

Macros
#define	ESP32_PIN_NUM_SHIFT   0U
	GPIO pin number field.
#define	ESP32_PIN_NUM_MASK   0x3FU
#define	ESP32_PIN_SIGI_MASK   0x1FFU
	Definitions used to extract I/O signal indexes.
#define	ESP32_PIN_SIGI_SHIFT   6U
#define	ESP32_PIN_SIGO_MASK   0x1FFU
#define	ESP32_PIN_SIGO_SHIFT   15U
#define	ESP_SIG_INVAL   ESP32_PIN_SIGI_MASK
#define	ESP32_PINMUX(pin, sig_i, sig_o)
	Construct ESP32 pinmux value from pin number and GPIO matrix signals.
#define	ESP32_RMII_SLOT_SHIFT   24U
	Ethernet RMII pin encoding.
#define	ESP32_RMII_SLOT_MASK   0xFU
	RMII signal slot field mask.
#define	ESP32_RMII_MARKER   BIT(30)
	Marks a cell as an RMII pinmux.
#define	ESP32_RMII_PINMUX(pin, slot)
	Construct an Ethernet RMII pinmux value.
Ethernet RMII signal slots
#define	ESP_RMII_CLK   0
	RMII reference clock.
#define	ESP_RMII_TX_EN   1
	RMII transmit enable.
#define	ESP_RMII_TXD0   2
	RMII transmit data 0.
#define	ESP_RMII_TXD1   3
	RMII transmit data 1.
#define	ESP_RMII_CRS_DV   4
	RMII carrier sense / data valid.
#define	ESP_RMII_RXD0   5
	RMII receive data 0.
#define	ESP_RMII_RXD1   6
	RMII receive data 1.
#define	ESP_RMII_SLOT_COUNT   7
	Number of ESP_RMII_* signal slots above.
ESP32 pin configuration bit field layout
ESP32 pin configuration bit field. This field encodes pin configuration options used by the ESP32 pinctrl driver. Fields: bias [ 0 : 1 ] drive [ 2 : 3 ] output level [ 4 : 5 ] input/output enable override [ 6 : 7 ] sleep hold [ 8 ] These values are combined into a single integer and later translated into GPIO configuration flags by the driver.
#define	ESP32_PIN_BIAS_SHIFT   0U
#define	ESP32_PIN_BIAS_MASK   0x3U
#define	ESP32_PIN_DRV_SHIFT   2U
#define	ESP32_PIN_DRV_MASK   0x3U
#define	ESP32_PIN_OUT_SHIFT   4U
#define	ESP32_PIN_OUT_MASK   0x3U
#define	ESP32_PIN_EN_DIR_SHIFT   6U
#define	ESP32_PIN_EN_DIR_MASK   0x3U
#define	ESP32_PIN_SLEEP_HOLD_SHIFT   8U
	Sleep hold bit.
#define	ESP32_PIN_SLEEP_HOLD_MASK   0x1U
	Sleep hold mask.
ESP32 pin bias configuration values
#define	ESP32_NO_PULL   0x1
#define	ESP32_PULL_UP   0x2
#define	ESP32_PULL_DOWN   0x3
ESP32 pin drive configuration values
#define	ESP32_PUSH_PULL   0x1
#define	ESP32_OPEN_DRAIN   0x2
ESP32 pin output level values
#define	ESP32_PIN_OUT_HIGH   0x1
#define	ESP32_PIN_OUT_LOW   0x2
ESP32 input/output enable override values
#define	ESP32_PIN_OUT_EN   0x1
#define	ESP32_PIN_IN_EN   0x2
ESP32 sleep hold configuration
#define	ESP32_PIN_SLEEP_HOLD_EN   0x1
	Sleep hold enable.
ESP32 pinctrl internal flags
Internal flags used by the ESP32 pinctrl driver. These flags are derived from the pin configuration bit field and control the GPIO driver behavior.
#define	ESP32_NO_PULL_FLAG   BIT(0)
#define	ESP32_PULL_UP_FLAG   BIT(1)
#define	ESP32_PULL_DOWN_FLAG   BIT(2)
#define	ESP32_PUSH_PULL_FLAG   BIT(3)
#define	ESP32_OPEN_DRAIN_FLAG   BIT(4)
#define	ESP32_DIR_INP_FLAG   BIT(5)
#define	ESP32_DIR_OUT_FLAG   BIT(6)
#define	ESP32_PIN_OUT_HIGH_FLAG   BIT(7)
#define	ESP32_PIN_OUT_LOW_FLAG   BIT(8)
#define	ESP32_PIN_OUT_EN_FLAG   BIT(9)
#define	ESP32_PIN_IN_EN_FLAG   BIT(10)
#define	ESP32_SLEEP_HOLD_FLAG   BIT(11)
	Sleep hold enable bit.

Macro Definition Documentation

ESP32_DIR_INP_FLAG

#define ESP32_DIR_INP_FLAG   BIT(5)

ESP32_DIR_OUT_FLAG

#define ESP32_DIR_OUT_FLAG   BIT(6)

ESP32_NO_PULL

#define ESP32_NO_PULL   0x1

ESP32_NO_PULL_FLAG

#define ESP32_NO_PULL_FLAG   BIT(0)

ESP32_OPEN_DRAIN

#define ESP32_OPEN_DRAIN   0x2

ESP32_OPEN_DRAIN_FLAG

#define ESP32_OPEN_DRAIN_FLAG   BIT(4)

ESP32_PIN_BIAS_MASK

#define ESP32_PIN_BIAS_MASK   0x3U

ESP32_PIN_BIAS_SHIFT

#define ESP32_PIN_BIAS_SHIFT   0U

ESP32_PIN_DRV_MASK

#define ESP32_PIN_DRV_MASK   0x3U

ESP32_PIN_DRV_SHIFT

#define ESP32_PIN_DRV_SHIFT   2U

ESP32_PIN_EN_DIR_MASK

#define ESP32_PIN_EN_DIR_MASK   0x3U

ESP32_PIN_EN_DIR_SHIFT

#define ESP32_PIN_EN_DIR_SHIFT   6U

ESP32_PIN_IN_EN

#define ESP32_PIN_IN_EN   0x2

ESP32_PIN_IN_EN_FLAG

#define ESP32_PIN_IN_EN_FLAG   BIT(10)

ESP32_PIN_NUM_MASK

#define ESP32_PIN_NUM_MASK   0x3FU

ESP32_PIN_NUM_SHIFT

#define ESP32_PIN_NUM_SHIFT   0U

GPIO pin number field.

ESP32_PIN_OUT_EN

#define ESP32_PIN_OUT_EN   0x1

ESP32_PIN_OUT_EN_FLAG

#define ESP32_PIN_OUT_EN_FLAG   BIT(9)

ESP32_PIN_OUT_HIGH

#define ESP32_PIN_OUT_HIGH   0x1

ESP32_PIN_OUT_HIGH_FLAG

#define ESP32_PIN_OUT_HIGH_FLAG   BIT(7)

ESP32_PIN_OUT_LOW

#define ESP32_PIN_OUT_LOW   0x2

ESP32_PIN_OUT_LOW_FLAG

#define ESP32_PIN_OUT_LOW_FLAG   BIT(8)

ESP32_PIN_OUT_MASK

#define ESP32_PIN_OUT_MASK   0x3U

ESP32_PIN_OUT_SHIFT

#define ESP32_PIN_OUT_SHIFT   4U

ESP32_PIN_SIGI_MASK

#define ESP32_PIN_SIGI_MASK   0x1FFU

Definitions used to extract I/O signal indexes.

These fields encode the GPIO matrix signal routing mechanism, allowing internal peripheral signals to be connected to GPIO pins.

ESP32_PIN_SIGI_SHIFT

#define ESP32_PIN_SIGI_SHIFT   6U

ESP32_PIN_SIGO_MASK

#define ESP32_PIN_SIGO_MASK   0x1FFU

ESP32_PIN_SIGO_SHIFT

#define ESP32_PIN_SIGO_SHIFT   15U

ESP32_PIN_SLEEP_HOLD_EN

#define ESP32_PIN_SLEEP_HOLD_EN   0x1

Sleep hold enable.

ESP32_PIN_SLEEP_HOLD_MASK

#define ESP32_PIN_SLEEP_HOLD_MASK   0x1U

Sleep hold mask.

ESP32_PIN_SLEEP_HOLD_SHIFT

#define ESP32_PIN_SLEEP_HOLD_SHIFT   8U

Sleep hold bit.

ESP32_PINMUX

#define ESP32_PINMUX	(		pin,
			sig_i,
			sig_o )

Value:

(((pin & ESP32_PIN_NUM_MASK) << ESP32_PIN_NUM_SHIFT) |                                     \
 ((sig_i & ESP32_PIN_SIGI_MASK) << ESP32_PIN_SIGI_SHIFT) |                                 \
 ((sig_o & ESP32_PIN_SIGO_MASK) << ESP32_PIN_SIGO_SHIFT))

Construct ESP32 pinmux value from pin number and GPIO matrix signals.

Parameters

pin	GPIO pin number
sig_i	Input signal index
sig_o	Output signal index

ESP32_PULL_DOWN

#define ESP32_PULL_DOWN   0x3

ESP32_PULL_DOWN_FLAG

#define ESP32_PULL_DOWN_FLAG   BIT(2)

ESP32_PULL_UP

#define ESP32_PULL_UP   0x2

ESP32_PULL_UP_FLAG

#define ESP32_PULL_UP_FLAG   BIT(1)

ESP32_PUSH_PULL

#define ESP32_PUSH_PULL   0x1

ESP32_PUSH_PULL_FLAG

#define ESP32_PUSH_PULL_FLAG   BIT(3)

ESP32_RMII_MARKER

#define ESP32_RMII_MARKER   BIT(30)

Marks a cell as an RMII pinmux.

ESP32_RMII_PINMUX

#define ESP32_RMII_PINMUX	(		pin,
			slot )

Value:

(ESP32_RMII_MARKER | (((slot) & ESP32_RMII_SLOT_MASK) << ESP32_RMII_SLOT_SHIFT) |          \
 (((pin) & ESP32_PIN_NUM_MASK) << ESP32_PIN_NUM_SHIFT))

Construct an Ethernet RMII pinmux value.

Parameters

pin	GPIO pin number
slot	RMII signal slot (ESP_RMII_*)

ESP32_RMII_SLOT_MASK

#define ESP32_RMII_SLOT_MASK   0xFU

RMII signal slot field mask.

ESP32_RMII_SLOT_SHIFT

#define ESP32_RMII_SLOT_SHIFT   24U

Ethernet RMII pin encoding.

RMII pads use dedicated EMAC IOMUX functions instead of the GPIO matrix, so they cannot use the ESP32_PINMUX() encoding. An RMII cell carries only the signal slot and GPIO number; the Ethernet driver resolves the IOMUX function and applies it. The ESP32_RMII_MARKER bit distinguishes these cells from ESP32_PINMUX() cells. RMII signal slot field shift

ESP32_SLEEP_HOLD_FLAG

#define ESP32_SLEEP_HOLD_FLAG   BIT(11)

Sleep hold enable bit.

ESP_RMII_CLK

#define ESP_RMII_CLK   0

RMII reference clock.

ESP_RMII_CRS_DV

#define ESP_RMII_CRS_DV   4

RMII carrier sense / data valid.

ESP_RMII_RXD0

#define ESP_RMII_RXD0   5

RMII receive data 0.

ESP_RMII_RXD1

#define ESP_RMII_RXD1   6

RMII receive data 1.

ESP_RMII_SLOT_COUNT

#define ESP_RMII_SLOT_COUNT   7

Number of ESP_RMII_* signal slots above.

ESP_RMII_TX_EN

#define ESP_RMII_TX_EN   1

RMII transmit enable.

ESP_RMII_TXD0

#define ESP_RMII_TXD0   2

RMII transmit data 0.

ESP_RMII_TXD1

#define ESP_RMII_TXD1   3

RMII transmit data 1.

ESP_SIG_INVAL

#define ESP_SIG_INVAL   ESP32_PIN_SIGI_MASK