cpu.h

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/*
 * Copyright 2025 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_
#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_
 
#include <zephyr/drivers/firmware/scmi/protocol.h>
#if __has_include("scmi_cpu_soc.h")
#include <scmi_cpu_soc.h>
#endif


#define SCMI_NXP_CPU_SLEEP_FLAG_IRQ_MUX 0x1U

#define SCMI_PROTOCOL_NXP_CPU_DOMAIN 130

#define SCMI_NXP_CPU_MAX_PDCONFIGS_T 7U

#define SCMI_NXP_CPU_IRQ_WAKE_NUM       22U

#define SCMI_NXP_CPU_VEC_FLAGS_BOOT    BIT(29)

#define SCMI_NXP_CPU_VEC_FLAGS_START   BIT(30)

#define SCMI_NXP_CPU_VEC_FLAGS_RESUME  BIT(31)

#define SCMI_NXP_CPU_PROTOCOL_SUPPORTED_VERSION 0x10000

struct scmi_nxp_cpu_sleep_mode_config {
        uint32_t cpu_id;
        uint32_t flags;
        uint32_t sleep_mode;
};

struct scmi_pd_lpm_settings {
        uint32_t domain_id;
        uint32_t lpm_setting;
        uint32_t ret_mask;
};

struct scmi_nxp_cpu_pd_lpm_config {
        uint32_t cpu_id;
        uint32_t num_cfg;
        struct scmi_pd_lpm_settings cfgs[SCMI_NXP_CPU_MAX_PDCONFIGS_T];
};

struct scmi_nxp_cpu_irq_mask_config {
        uint32_t cpu_id;
        uint32_t mask_idx;
        uint32_t num_mask;
        uint32_t mask[SCMI_NXP_CPU_IRQ_WAKE_NUM];
};

struct scmi_nxp_cpu_vector_config {
        uint32_t cpu_id;
        uint32_t flags;
        uint32_t vector_low;
        uint32_t vector_high;
};

struct scmi_nxp_cpu_info {
        uint32_t run_mode;
        uint32_t sleep_mode;
        uint32_t vector_low;
        uint32_t vector_high;
};

int scmi_nxp_cpu_sleep_mode_set(struct scmi_nxp_cpu_sleep_mode_config *cfg);

int scmi_nxp_cpu_pd_lpm_set(struct scmi_nxp_cpu_pd_lpm_config *cfg);

int scmi_nxp_cpu_set_irq_mask(struct scmi_nxp_cpu_irq_mask_config *cfg);

int scmi_nxp_cpu_reset_vector(struct scmi_nxp_cpu_vector_config *cfg);

int scmi_nxp_cpu_info_get(uint32_t cpu_id, struct scmi_nxp_cpu_info *cfg);

 
#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_ */