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4.2.0-rc3
A Scalable Open Source RTOS
4.2.0-rc3
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dma_stm32.h
Go to the documentation of this file.
1
/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_STM32_H_
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#define ZEPHYR_INCLUDE_DRIVERS_DMA_STM32_H_
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/* @brief linked_channel value to inform zephyr dma driver that
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* DMA channel will be handled by HAL
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*/
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#define STM32_DMA_HAL_OVERRIDE 0x7F
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/* @brief gives the first DMA channel : 0 or 1 in the register map
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* when counting channels from 1 to N or from 0 to N-1
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*/
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#if defined(CONFIG_DMA_STM32U5)
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/* from DTS the dma stream id is in range 0..N-1 */
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#define STM32_DMA_STREAM_OFFSET 0
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#elif !defined(CONFIG_DMA_STM32_V1)
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/* from DTS the dma stream id is in range 1..N */
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/* so decrease to set range from 0 from now on */
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#define STM32_DMA_STREAM_OFFSET 1
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#elif defined(CONFIG_DMA_STM32_V1) && defined(CONFIG_DMAMUX_STM32)
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/* typically on the stm32H7 series, DMA V1 with mux */
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#define STM32_DMA_STREAM_OFFSET 1
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#else
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/* from DTS the dma stream id is in range 0..N-1 */
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#define STM32_DMA_STREAM_OFFSET 0
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#endif
/* ! CONFIG_DMA_STM32_V1 */
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/* macro for dma slot (only for dma-v1 or dma-v2 types) */
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v2bis)
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#define STM32_DMA_SLOT(id, dir, slot) 0
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#define STM32_DMA_SLOT_BY_IDX(id, idx, slot) 0
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#else
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#define STM32_DMA_SLOT(id, dir, slot) DT_INST_DMAS_CELL_BY_NAME(id, dir, slot)
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#define STM32_DMA_SLOT_BY_IDX(id, idx, slot) DT_INST_DMAS_CELL_BY_IDX(id, idx, slot)
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v2) || \
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DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v2bis) || \
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DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dmamux)
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#define STM32_DMA_FEATURES(id, dir) 0
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#else
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#define STM32_DMA_FEATURES(id, dir) \
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DT_INST_DMAS_CELL_BY_NAME(id, dir, features)
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#define STM32_DMA_FEATURES(id, dir) \
…
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#endif
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#define STM32_DMA_CTLR(id, dir) \
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DT_INST_DMAS_CTLR_BY_NAME(id, dir)
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#define STM32_DMA_CTLR(id, dir) \
…
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#define STM32_DMA_CHANNEL_CONFIG(id, dir) \
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DT_INST_DMAS_CELL_BY_NAME(id, dir, channel_config)
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#define STM32_DMA_CHANNEL_CONFIG(id, dir) \
…
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#define STM32_DMA_CHANNEL_CONFIG_BY_IDX(id, idx) \
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DT_INST_DMAS_CELL_BY_IDX(id, idx, channel_config)
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#define STM32_DMA_CHANNEL_CONFIG_BY_IDX(id, idx) \
…
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/* macros for channel-config */
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/* enable circular buffer */
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#define STM32_DMA_CONFIG_CYCLIC(config) ((config >> 5) & 0x1)
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/* direction defined on bits 6-7 */
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/* 0 -> MEM_TO_MEM, 1 -> MEM_TO_PERIPH, 2 -> PERIPH_TO_MEM */
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#define STM32_DMA_CONFIG_DIRECTION(config) ((config >> 6) & 0x3)
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/* periph increment defined on bit 9 as true/false */
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#define STM32_DMA_CONFIG_PERIPHERAL_ADDR_INC(config) ((config >> 9) & 0x1)
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/* mem increment defined on bit 10 as true/false */
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#define STM32_DMA_CONFIG_MEMORY_ADDR_INC(config) ((config >> 10) & 0x1)
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/* periph data size defined on bits 11-12 */
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/* 0 -> 1 byte, 1 -> 2 bytes, 2 -> 4 bytes */
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#define STM32_DMA_CONFIG_PERIPHERAL_DATA_SIZE(config) \
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(1 << ((config >> 11) & 0x3))
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#define STM32_DMA_CONFIG_PERIPHERAL_DATA_SIZE(config) \
…
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/* memory data size defined on bits 13, 14 */
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/* 0 -> 1 byte, 1 -> 2 bytes, 2 -> 4 bytes */
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#define STM32_DMA_CONFIG_MEMORY_DATA_SIZE(config) \
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(1 << ((config >> 13) & 0x3))
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#define STM32_DMA_CONFIG_MEMORY_DATA_SIZE(config) \
…
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/* priority increment offset defined on bit 15 */
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#define STM32_DMA_CONFIG_PERIPHERAL_INC_FIXED(config) ((config >> 15) & 0x1)
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/* priority defined on bits 16-17 as 0, 1, 2, 3 */
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#define STM32_DMA_CONFIG_PRIORITY(config) ((config >> 16) & 0x3)
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/* macro for features (only for dma-v1) */
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v1)
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#define STM32_DMA_FEATURES_FIFO_THRESHOLD(features) (features & 0x3)
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#else
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#define STM32_DMA_FEATURES_FIFO_THRESHOLD(features) 0
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#endif
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#endif
/* ZEPHYR_INCLUDE_DRIVERS_DMA_STM32_H_ */
zephyr
drivers
dma
dma_stm32.h
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