Zephyr API Documentation 4.0.0-rc2
A Scalable Open Source RTOS
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ccc.h
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1/*
2 * Copyright 2022 Intel Corporation
3 * Copyright 2023 Meta Platforms, Inc. and its affiliates
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_
9#define ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_
10
18#include <stdint.h>
19
20#include <zephyr/device.h>
21#include <zephyr/toolchain.h>
22#include <zephyr/sys/util.h>
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
29#define I3C_CCC_BROADCAST_MAX_ID 0x7FU
30
36#define I3C_CCC_ENEC(broadcast) ((broadcast) ? 0x00U : 0x80U)
37
43#define I3C_CCC_DISEC(broadcast) ((broadcast) ? 0x01U : 0x81U)
44
51#define I3C_CCC_ENTAS(as, broadcast) (((broadcast) ? 0x02U : 0x82U) + (as))
52
58#define I3C_CCC_ENTAS0(broadcast) I3C_CCC_ENTAS(0, broadcast)
59
65#define I3C_CCC_ENTAS1(broadcast) I3C_CCC_ENTAS(1, broadcast)
66
72#define I3C_CCC_ENTAS2(broadcast) I3C_CCC_ENTAS(2, broadcast)
73
79#define I3C_CCC_ENTAS3(broadcast) I3C_CCC_ENTAS(3, broadcast)
80
82#define I3C_CCC_RSTDAA 0x06U
83
85#define I3C_CCC_ENTDAA 0x07U
86
88#define I3C_CCC_DEFTGTS 0x08U
89
95#define I3C_CCC_SETMWL(broadcast) ((broadcast) ? 0x09U : 0x89U)
96
102#define I3C_CCC_SETMRL(broadcast) ((broadcast) ? 0x0AU : 0x8AU)
103
105#define I3C_CCC_ENTTM 0x0BU
106
108#define I3C_CCC_SETBUSCON 0x0CU
109
115#define I3C_CCC_ENDXFER(broadcast) ((broadcast) ? 0x12U : 0x92U)
116
118#define I3C_CCC_ENTHDR(x) (0x20U + (x))
119
121#define I3C_CCC_ENTHDR0 0x20U
122
124#define I3C_CCC_ENTHDR1 0x21U
125
127#define I3C_CCC_ENTHDR2 0x22U
128
130#define I3C_CCC_ENTHDR3 0x23U
131
133#define I3C_CCC_ENTHDR4 0x24U
134
136#define I3C_CCC_ENTHDR5 0x25U
137
139#define I3C_CCC_ENTHDR6 0x26U
140
142#define I3C_CCC_ENTHDR7 0x27U
143
149#define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28U : 0x98U)
150
152#define I3C_CCC_SETAASA 0x29U
153
159#define I3C_CCC_RSTACT(broadcast) ((broadcast) ? 0x2AU : 0x9AU)
160
162#define I3C_CCC_DEFGRPA 0x2BU
163
169#define I3C_CCC_RSTGRPA(broadcast) ((broadcast) ? 0x2CU : 0x9CU)
170
172#define I3C_CCC_MLANE(broadcast) ((broadcast) ? 0x2DU : 0x9DU)
173
180#define I3C_CCC_VENDOR(broadcast, id) ((id) + ((broadcast) ? 0x61U : 0xE0U))
181
183#define I3C_CCC_SETDASA 0x87U
184
186#define I3C_CCC_SETNEWDA 0x88U
187
189#define I3C_CCC_GETMWL 0x8BU
190
192#define I3C_CCC_GETMRL 0x8CU
193
195#define I3C_CCC_GETPID 0x8DU
196
198#define I3C_CCC_GETBCR 0x8EU
199
201#define I3C_CCC_GETDCR 0x8FU
202
204#define I3C_CCC_GETSTATUS 0x90U
205
207#define I3C_CCC_GETACCCR 0x91U
208
210#define I3C_CCC_SETBRGTGT 0x93U
211
213#define I3C_CCC_GETMXDS 0x94U
214
216#define I3C_CCC_GETCAPS 0x95U
217
219#define I3C_CCC_SETROUTE 0x96U
220
222#define I3C_CCC_D2DXFER 0x97U
223
225#define I3C_CCC_GETXTIME 0x99U
226
228#define I3C_CCC_SETGRPA 0x9BU
229
230struct i3c_device_desc;
231
263
268 struct {
273
281
283 size_t data_len;
284
291 size_t num_xfer;
293
294 struct {
304
308};
309
324} __packed;
325
327#define I3C_CCC_ENEC_EVT_ENINTR BIT(0)
328
330#define I3C_CCC_ENEC_EVT_ENCR BIT(1)
331
333#define I3C_CCC_ENEC_EVT_ENHJ BIT(3)
334
335#define I3C_CCC_ENEC_EVT_ALL \
336 (I3C_CCC_ENEC_EVT_ENINTR | I3C_CCC_ENEC_EVT_ENCR | I3C_CCC_ENEC_EVT_ENHJ)
337
339#define I3C_CCC_DISEC_EVT_DISINTR BIT(0)
340
342#define I3C_CCC_DISEC_EVT_DISCR BIT(1)
343
345#define I3C_CCC_DISEC_EVT_DISHJ BIT(3)
346
347#define I3C_CCC_DISEC_EVT_ALL \
348 (I3C_CCC_DISEC_EVT_DISINTR | I3C_CCC_DISEC_EVT_DISCR | I3C_CCC_DISEC_EVT_DISHJ)
349
350/*
351 * Events for both enabling and disabling since
352 * they have the same bits.
353 */
354
356#define I3C_CCC_EVT_INTR BIT(0)
357
359#define I3C_CCC_EVT_CR BIT(1)
360
362#define I3C_CCC_EVT_HJ BIT(3)
363
365#define I3C_CCC_EVT_ALL \
366 (I3C_CCC_EVT_INTR | I3C_CCC_EVT_CR | I3C_CCC_EVT_HJ)
367
379} __packed;
380
392
395} __packed;
396
416
444
463
476
506} __packed;
507
518} __packed;
519
526} __packed;
527
534} __packed;
535
536
547
561
566 struct {
582
583 union {
590
604
607} __packed;
608
610#define I3C_CCC_GETSTATUS_PROTOCOL_ERR BIT(5)
611
613#define I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK GENMASK(7U, 6U)
614
623#define I3C_CCC_GETSTATUS_ACTIVITY_MODE(status) \
624 FIELD_GET(I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK, (status))
625
627#define I3C_CCC_GETSTATUS_NUM_INT_MASK GENMASK(3U, 0U)
628
637#define I3C_CCC_GETSTATUS_NUM_INT(status) \
638 FIELD_GET(I3C_CCC_GETSTATUS_NUM_INT_MASK, (status))
639
641#define I3C_CCC_GETSTATUS_PRECR_DEEP_SLEEP_DETECTED BIT(0)
642
644#define I3C_CCC_GETSTATUS_PRECR_HANDOFF_DELAY_NACK BIT(1)
645
668
683
697
714
715
720 struct {
723
727
728 struct {
731
734
742
743 struct {
750
758} __packed;
759
761#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_MAX 0
762
764#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_8MHZ 1
765
767#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_6MHZ 2
768
770#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_4MHZ 3
771
773#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_2MHZ 4
774
776#define I3C_CCC_GETMXDS_TSCO_8NS 0
777
779#define I3C_CCC_GETMXDS_TSCO_9NS 1
780
782#define I3C_CCC_GETMXDS_TSCO_10NS 2
783
785#define I3C_CCC_GETMXDS_TSCO_11NS 3
786
788#define I3C_CCC_GETMXDS_TSCO_12NS 4
789
791#define I3C_CCC_GETMXDS_TSCO_GT_12NS 7
792
794#define I3C_CCC_GETMXDS_MAXWR_DEFINING_BYTE_SUPPORT BIT(3)
795
797#define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK GENMASK(2U, 0U)
798
807#define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL(maxwr) \
808 FIELD_GET(I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK, (maxwr))
809
811#define I3C_CCC_GETMXDS_MAXRD_W2R_PERMITS_STOP_BETWEEN BIT(6)
812
814#define I3C_CCC_GETMXDS_MAXRD_TSCO_MASK GENMASK(5U, 3U)
815
824#define I3C_CCC_GETMXDS_MAXRD_TSCO(maxrd) \
825 FIELD_GET(I3C_CCC_GETMXDS_MAXRD_TSCO_MASK, (maxrd))
826
828#define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK GENMASK(2U, 0U)
829
838#define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL(maxrd) \
839 FIELD_GET(I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK, (maxrd))
840
842#define I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE BIT(2)
843
845#define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK GENMASK(1U, 0U)
846
855#define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE(crhdly1) \
856 FIELD_GET(I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK, (chrdly1))
857
868
891
900 union {
909
937
938 union {
945
952
966
980} __packed;
981
983#define I3C_CCC_GETCAPS1_HDR_DDR BIT(0)
984
986#define I3C_CCC_GETCAPS1_HDR_TSP BIT(1)
987
989#define I3C_CCC_GETCAPS1_HDR_TSL BIT(2)
990
992#define I3C_CCC_GETCAPS1_HDR_BT BIT(3)
993
1001#define I3C_CCC_GETCAPS1_HDR_MODE(x) BIT(x)
1002
1004#define I3C_CCC_GETCAPS1_HDR_MODE0 BIT(0)
1005
1007#define I3C_CCC_GETCAPS1_HDR_MODE1 BIT(1)
1008
1010#define I3C_CCC_GETCAPS1_HDR_MODE2 BIT(2)
1011
1013#define I3C_CCC_GETCAPS1_HDR_MODE3 BIT(3)
1014
1016#define I3C_CCC_GETCAPS1_HDR_MODE4 BIT(4)
1017
1019#define I3C_CCC_GETCAPS1_HDR_MODE5 BIT(5)
1020
1022#define I3C_CCC_GETCAPS1_HDR_MODE6 BIT(6)
1023
1025#define I3C_CCC_GETCAPS1_HDR_MODE7 BIT(7)
1026
1028#define I3C_CCC_GETCAPS2_HDRDDR_WRITE_ABORT BIT(6)
1029
1031#define I3C_CCC_GETCAPS2_HDRDDR_ABORT_CRC BIT(7)
1032
1037#define I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK GENMASK(5U, 4U)
1038
1047#define I3C_CCC_GETCAPS2_GRPADDR_CAP(getcaps2) \
1048 FIELD_GET(I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK, (getcaps2))
1049
1054#define I3C_CCC_GETCAPS2_SPEC_VER_MASK GENMASK(3U, 0U)
1055
1065#define I3C_CCC_GETCAPS2_SPEC_VER(getcaps2) \
1066 FIELD_GET(I3C_CCC_GETCAPS2_SPEC_VER_MASK, (getcaps2))
1067
1072#define I3C_CCC_GETCAPS3_MLANE_SUPPORT BIT(0)
1073
1078#define I3C_CCC_GETCAPS3_D2DXFER_SUPPORT BIT(1)
1079
1084#define I3C_CCC_GETCAPS3_D2DXFER_IBI_CAPABLE BIT(2)
1085
1090#define I3C_CCC_GETCAPS3_GETCAPS_DEFINING_BYTE_SUPPORT BIT(3)
1091
1096#define I3C_CCC_GETCAPS3_GETSTATUS_DEFINING_BYTE_SUPPORT BIT(4)
1097
1102#define I3C_CCC_GETCAPS3_HDRBT_CRC32_SUPPORT BIT(5)
1103
1108#define I3C_CCC_GETCAPS3_IBI_MDR_PENDING_READ_NOTIFICATION BIT(6)
1109
1114#define I3C_CCC_GETCAPS_TESTPAT1 0xA5
1115
1120#define I3C_CCC_GETCAPS_TESTPAT2 0x5A
1121
1126#define I3C_CCC_GETCAPS_TESTPAT3 0xA5
1127
1132#define I3C_CCC_GETCAPS_TESTPAT4 0x5A
1133
1138#define I3C_CCC_GETCAPS_TESTPAT 0xA55AA55A
1139
1144#define I3C_CCC_GETCAPS_CRCAPS1_HJ_SUPPORT BIT(0)
1145
1150#define I3C_CCC_GETCAPS_CRCAPS1_GRP_MANAGEMENT_SUPPORT BIT(1)
1151
1156#define I3C_CCC_GETCAPS_CRCAPS1_ML_SUPPORT BIT(2)
1157
1162#define I3C_CCC_GETCAPS_CRCAPS2_IBI_TIR_SUPPORT BIT(0)
1163
1168#define I3C_CCC_GETCAPS_CRCAPS2_CONTROLLER_PASSBACK BIT(1)
1169
1174#define I3C_CCC_GETCAPS_CRCAPS2_DEEP_SLEEP_CAPABLE BIT(2)
1175
1180#define I3C_CCC_GETCAPS_CRCAPS2_DELAYED_CONTROLLER_HANDOFF BIT(3)
1181
1183#define I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_MASK GENMASK(2U, 0U)
1184
1193#define I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE(vtcap1) \
1194 FIELD_GET(I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_MASK, (vtcap1))
1195
1200#define I3C_CCC_GETCAPS_VTCAP1_SIDE_EFFECTS BIT(4)
1201
1206#define I3C_CCC_GETCAPS_VTCAP1_SHARED_PERIPH_DETECT BIT(5)
1207
1209#define I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_MASK GENMASK(1U, 0U)
1210
1219#define I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS(vtcap2) \
1220 FIELD_GET(I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_MASK, (vtcap2))
1221
1226#define I3C_CCC_GETCAPS_VTCAP2_ADDRESS_REMAPPING BIT(2)
1227
1229#define I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_MASK GENMASK(4U, 3U)
1230
1239#define I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND(vtcap2) \
1240 FIELD_GET(I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_MASK, (vtcap2))
1241
1273
1302#define I3C_CCC_SETBUSCON_I3C_SPEC_MINOR_VER_MASK GENMASK(3U, 0U)
1303
1311#define I3C_CCC_SETBUSCON_I3C_SPEC_MINOR_VER(y) \
1312 FIELD_PREP(I3C_CCC_SETBUSCON_I3C_SPEC_MINOR_VER_MASK, (y))
1313
1315#define I3C_CCC_SETBUSCON_I3C_SPEC_I3C_SPEC 0
1316
1318#define I3C_CCC_SETBUSCON_I3C_SPEC_I3C_BASIC_SPEC BIT(4)
1319
1321#define I3C_CCC_SETBUSCON_I3C_SPEC_I3C_SPEC_EDITORIAL_1_Y_0 0
1322
1324#define I3C_CCC_SETBUSCON_I3C_SPEC_I3C_SPEC_EDITORIAL_1_Y_1 BIT(5)
1325
1340#define I3C_CCC_SETBUSCON_OTHER_STANDARDS_JEDEC_SIDEBAND 128
1341
1349#define I3C_CCC_SETBUSCON_OTHER_STANDARDS_MCTP 129
1350
1357#define I3C_CCC_SETBUSCON_OTHER_STANDARDS_ETSI 130
1358
1371static inline bool i3c_ccc_is_payload_broadcast(const struct i3c_ccc_payload *payload)
1372{
1373 return (payload->ccc.id <= I3C_CCC_BROADCAST_MAX_ID);
1374}
1375
1388 struct i3c_ccc_getbcr *bcr);
1389
1402 struct i3c_ccc_getdcr *dcr);
1403
1416 struct i3c_ccc_getpid *pid);
1417
1429int i3c_ccc_do_rstact_all(const struct device *controller,
1430 enum i3c_ccc_rstact_defining_byte action);
1431
1445int i3c_ccc_do_rstact(const struct i3c_device_desc *target,
1446 enum i3c_ccc_rstact_defining_byte action,
1447 bool get,
1448 uint8_t *data);
1449
1461static inline int i3c_ccc_do_rstact_fmt2(const struct i3c_device_desc *target,
1462 enum i3c_ccc_rstact_defining_byte action)
1463{
1464 return i3c_ccc_do_rstact(target, action, false, NULL);
1465}
1466
1479static inline int i3c_ccc_do_rstact_fmt3(const struct i3c_device_desc *target,
1480 enum i3c_ccc_rstact_defining_byte action,
1481 uint8_t *data)
1482{
1483 return i3c_ccc_do_rstact(target, action, true, data);
1484}
1485
1495int i3c_ccc_do_rstdaa_all(const struct device *controller);
1496
1511int i3c_ccc_do_setdasa(const struct i3c_device_desc *target,
1512 struct i3c_ccc_address da);
1513
1527int i3c_ccc_do_setnewda(const struct i3c_device_desc *target,
1528 struct i3c_ccc_address new_da);
1529
1542int i3c_ccc_do_events_all_set(const struct device *controller,
1543 bool enable, struct i3c_ccc_events *events);
1544
1558 bool enable, struct i3c_ccc_events *events);
1559
1571int i3c_ccc_do_entas(const struct i3c_device_desc *target, uint8_t as);
1572
1583static inline int i3c_ccc_do_entas0(const struct i3c_device_desc *target)
1584{
1585 return i3c_ccc_do_entas(target, 0);
1586}
1587
1598static inline int i3c_ccc_do_entas1(const struct i3c_device_desc *target)
1599{
1600 return i3c_ccc_do_entas(target, 1);
1601}
1602
1613static inline int i3c_ccc_do_entas2(const struct i3c_device_desc *target)
1614{
1615 return i3c_ccc_do_entas(target, 2);
1616}
1617
1628static inline int i3c_ccc_do_entas3(const struct i3c_device_desc *target)
1629{
1630 return i3c_ccc_do_entas(target, 3);
1631}
1632
1643int i3c_ccc_do_entas_all(const struct device *controller, uint8_t as);
1644
1654static inline int i3c_ccc_do_entas0_all(const struct device *controller)
1655{
1656 return i3c_ccc_do_entas_all(controller, 0);
1657}
1658
1668static inline int i3c_ccc_do_entas1_all(const struct device *controller)
1669{
1670 return i3c_ccc_do_entas_all(controller, 1);
1671}
1672
1682static inline int i3c_ccc_do_entas2_all(const struct device *controller)
1683{
1684 return i3c_ccc_do_entas_all(controller, 2);
1685}
1686
1696static inline int i3c_ccc_do_entas3_all(const struct device *controller)
1697{
1698 return i3c_ccc_do_entas_all(controller, 3);
1699}
1700
1712int i3c_ccc_do_setmwl_all(const struct device *controller,
1713 const struct i3c_ccc_mwl *mwl);
1714
1726int i3c_ccc_do_setmwl(const struct i3c_device_desc *target,
1727 const struct i3c_ccc_mwl *mwl);
1728
1740int i3c_ccc_do_getmwl(const struct i3c_device_desc *target,
1741 struct i3c_ccc_mwl *mwl);
1742
1756int i3c_ccc_do_setmrl_all(const struct device *controller,
1757 const struct i3c_ccc_mrl *mrl,
1758 bool has_ibi_size);
1759
1774int i3c_ccc_do_setmrl(const struct i3c_device_desc *target,
1775 const struct i3c_ccc_mrl *mrl);
1776
1791int i3c_ccc_do_getmrl(const struct i3c_device_desc *target,
1792 struct i3c_ccc_mrl *mrl);
1793
1804int i3c_ccc_do_enttm(const struct device *controller,
1805 enum i3c_ccc_enttm_defbyte defbyte);
1806
1823int i3c_ccc_do_getstatus(const struct i3c_device_desc *target,
1824 union i3c_ccc_getstatus *status,
1825 enum i3c_ccc_getstatus_fmt fmt,
1826 enum i3c_ccc_getstatus_defbyte defbyte);
1827
1839static inline int i3c_ccc_do_getstatus_fmt1(const struct i3c_device_desc *target,
1840 union i3c_ccc_getstatus *status)
1841{
1842 return i3c_ccc_do_getstatus(target, status,
1845}
1846
1859static inline int i3c_ccc_do_getstatus_fmt2(const struct i3c_device_desc *target,
1860 union i3c_ccc_getstatus *status,
1861 enum i3c_ccc_getstatus_defbyte defbyte)
1862{
1863 return i3c_ccc_do_getstatus(target, status,
1864 GETSTATUS_FORMAT_2, defbyte);
1865}
1866
1883int i3c_ccc_do_getcaps(const struct i3c_device_desc *target,
1884 union i3c_ccc_getcaps *caps,
1885 enum i3c_ccc_getcaps_fmt fmt,
1886 enum i3c_ccc_getcaps_defbyte defbyte);
1887
1899static inline int i3c_ccc_do_getcaps_fmt1(const struct i3c_device_desc *target,
1900 union i3c_ccc_getcaps *caps)
1901{
1902 return i3c_ccc_do_getcaps(target, caps,
1905}
1906
1919static inline int i3c_ccc_do_getcaps_fmt2(const struct i3c_device_desc *target,
1920 union i3c_ccc_getcaps *caps,
1921 enum i3c_ccc_getcaps_defbyte defbyte)
1922{
1923 return i3c_ccc_do_getcaps(target, caps,
1924 GETCAPS_FORMAT_2, defbyte);
1925}
1926
1940int i3c_ccc_do_setvendor(const struct i3c_device_desc *target,
1941 uint8_t id,
1942 uint8_t *payload,
1943 size_t len);
1944
1959int i3c_ccc_do_getvendor(const struct i3c_device_desc *target,
1960 uint8_t id,
1961 uint8_t *payload,
1962 size_t len,
1963 size_t *num_xfer);
1964
1982 uint8_t id,
1983 uint8_t defbyte,
1984 uint8_t *payload,
1985 size_t len,
1986 size_t *num_xfer);
1987
2000int i3c_ccc_do_setvendor_all(const struct device *controller,
2001 uint8_t id,
2002 uint8_t *payload,
2003 size_t len);
2004
2016int i3c_ccc_do_setaasa_all(const struct device *controller);
2017
2034int i3c_ccc_do_getmxds(const struct i3c_device_desc *target,
2035 union i3c_ccc_getmxds *caps,
2036 enum i3c_ccc_getmxds_fmt fmt,
2037 enum i3c_ccc_getmxds_defbyte defbyte);
2038
2050static inline int i3c_ccc_do_getmxds_fmt1(const struct i3c_device_desc *target,
2051 union i3c_ccc_getmxds *caps)
2052{
2053 return i3c_ccc_do_getmxds(target, caps,
2056}
2057
2069static inline int i3c_ccc_do_getmxds_fmt2(const struct i3c_device_desc *target,
2070 union i3c_ccc_getmxds *caps)
2071{
2072 return i3c_ccc_do_getmxds(target, caps,
2075}
2076
2089static inline int i3c_ccc_do_getmxds_fmt3(const struct i3c_device_desc *target,
2090 union i3c_ccc_getmxds *caps,
2091 enum i3c_ccc_getmxds_defbyte defbyte)
2092{
2093 return i3c_ccc_do_getmxds(target, caps,
2094 GETMXDS_FORMAT_3, defbyte);
2095}
2096
2105int i3c_ccc_do_deftgts_all(const struct device *controller,
2106 struct i3c_ccc_deftgts *deftgts);
2107
2119int i3c_ccc_do_setbuscon(const struct device *controller,
2120 uint8_t *context, uint16_t length);
2121
2122#ifdef __cplusplus
2123}
2124#endif
2125
2130#endif /* ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_ */
irp nz macro MOVR cc s mov cc s endm endr irp as
Definition asm-macro-32-bit-gnu.h:16
static int i3c_ccc_do_entas0_all(const struct device *controller)
Broadcast ENTAS0.
Definition ccc.h:1654
int i3c_ccc_do_deftgts_all(const struct device *controller, struct i3c_ccc_deftgts *deftgts)
Broadcast DEFTGTS.
i3c_ccc_getstatus_defbyte
Defining byte values for GETSTATUS Format 2.
Definition ccc.h:551
i3c_ccc_getmxds_fmt
Indicate which format of getmxds to use.
Definition ccc.h:687
static int i3c_ccc_do_getstatus_fmt1(const struct i3c_device_desc *target, union i3c_ccc_getstatus *status)
Single target GETSTATUS to Get Target Status (Format 1).
Definition ccc.h:1839
int i3c_ccc_do_setmrl_all(const struct device *controller, const struct i3c_ccc_mrl *mrl, bool has_ibi_size)
Broadcast SETMRL to Set Maximum Read Length.
int i3c_ccc_do_getvendor(const struct i3c_device_desc *target, uint8_t id, uint8_t *payload, size_t len, size_t *num_xfer)
Single target to Get Vendor / Standard Extension CCC.
static int i3c_ccc_do_entas3(const struct i3c_device_desc *target)
Direct ENTAS3.
Definition ccc.h:1628
i3c_ccc_enttm_defbyte
Defining byte values for ENTTM.
Definition ccc.h:467
int i3c_ccc_do_rstact_all(const struct device *controller, enum i3c_ccc_rstact_defining_byte action)
Broadcast RSTACT to reset I3C Peripheral (Format 1).
int i3c_ccc_do_getvendor_defbyte(const struct i3c_device_desc *target, uint8_t id, uint8_t defbyte, uint8_t *payload, size_t len, size_t *num_xfer)
Single target to Get Vendor / Standard Extension CCC with a defining byte.
static int i3c_ccc_do_getstatus_fmt2(const struct i3c_device_desc *target, union i3c_ccc_getstatus *status, enum i3c_ccc_getstatus_defbyte defbyte)
Single target GETSTATUS to Get Target Status (Format 2).
Definition ccc.h:1859
int i3c_ccc_do_getstatus(const struct i3c_device_desc *target, union i3c_ccc_getstatus *status, enum i3c_ccc_getstatus_fmt fmt, enum i3c_ccc_getstatus_defbyte defbyte)
Single target GETSTATUS to Get Target Status.
static int i3c_ccc_do_getmxds_fmt3(const struct i3c_device_desc *target, union i3c_ccc_getmxds *caps, enum i3c_ccc_getmxds_defbyte defbyte)
Single target GETMXDS to Get Max Data Speed (Format 3).
Definition ccc.h:2089
static int i3c_ccc_do_getmxds_fmt2(const struct i3c_device_desc *target, union i3c_ccc_getmxds *caps)
Single target GETMXDS to Get Max Data Speed (Format 2).
Definition ccc.h:2069
int i3c_ccc_do_enttm(const struct device *controller, enum i3c_ccc_enttm_defbyte defbyte)
Broadcast ENTTM.
static int i3c_ccc_do_entas1(const struct i3c_device_desc *target)
Direct ENTAS1.
Definition ccc.h:1598
i3c_ccc_getmxds_defbyte
Enum for I3C Get Max Data Speed (GETMXDS) Format 3 Defining Byte Values.
Definition ccc.h:701
i3c_ccc_rstact_defining_byte
Enum for I3C Reset Action (RSTACT) Defining Byte Values.
Definition ccc.h:1245
int i3c_ccc_do_setmwl_all(const struct device *controller, const struct i3c_ccc_mwl *mwl)
Broadcast SETMWL to Set Maximum Write Length.
int i3c_ccc_do_entas(const struct i3c_device_desc *target, uint8_t as)
Direct ENTAS to set the Activity State.
int i3c_ccc_do_getmxds(const struct i3c_device_desc *target, union i3c_ccc_getmxds *caps, enum i3c_ccc_getmxds_fmt fmt, enum i3c_ccc_getmxds_defbyte defbyte)
Single target GETMXDS to Get Max Data Speed.
int i3c_ccc_do_setnewda(const struct i3c_device_desc *target, struct i3c_ccc_address new_da)
Set New Dynamic Address for a target.
int i3c_ccc_do_setmrl(const struct i3c_device_desc *target, const struct i3c_ccc_mrl *mrl)
Single target SETMRL to Set Maximum Read Length.
int i3c_ccc_do_setbuscon(const struct device *controller, uint8_t *context, uint16_t length)
Broadcast SETBUSCON to set the bus context.
int i3c_ccc_do_setvendor(const struct i3c_device_desc *target, uint8_t id, uint8_t *payload, size_t len)
Single target to Set Vendor / Standard Extension CCC.
i3c_ccc_getstatus_fmt
Indicate which format of GETSTATUS to use.
Definition ccc.h:540
int i3c_ccc_do_setvendor_all(const struct device *controller, uint8_t id, uint8_t *payload, size_t len)
Broadcast Set Vendor / Standard Extension CCC.
int i3c_ccc_do_getbcr(struct i3c_device_desc *target, struct i3c_ccc_getbcr *bcr)
Get BCR from a target.
int i3c_ccc_do_getdcr(struct i3c_device_desc *target, struct i3c_ccc_getdcr *dcr)
Get DCR from a target.
int i3c_ccc_do_rstact(const struct i3c_device_desc *target, enum i3c_ccc_rstact_defining_byte action, bool get, uint8_t *data)
Single target RSTACT to reset I3C Peripheral.
static int i3c_ccc_do_entas1_all(const struct device *controller)
Broadcast ENTAS1.
Definition ccc.h:1668
int i3c_ccc_do_getpid(struct i3c_device_desc *target, struct i3c_ccc_getpid *pid)
Get PID from a target.
int i3c_ccc_do_getcaps(const struct i3c_device_desc *target, union i3c_ccc_getcaps *caps, enum i3c_ccc_getcaps_fmt fmt, enum i3c_ccc_getcaps_defbyte defbyte)
Single target GETCAPS to Get Target Status.
int i3c_ccc_do_entas_all(const struct device *controller, uint8_t as)
Broadcast ENTAS to set the Activity State.
i3c_ccc_getcaps_fmt
Indicate which format of GETCAPS to use.
Definition ccc.h:861
static int i3c_ccc_do_getmxds_fmt1(const struct i3c_device_desc *target, union i3c_ccc_getmxds *caps)
Single target GETMXDS to Get Max Data Speed (Format 1).
Definition ccc.h:2050
static int i3c_ccc_do_getcaps_fmt2(const struct i3c_device_desc *target, union i3c_ccc_getcaps *caps, enum i3c_ccc_getcaps_defbyte defbyte)
Single target GETCAPS to Get Capabilities (Format 2).
Definition ccc.h:1919
static bool i3c_ccc_is_payload_broadcast(const struct i3c_ccc_payload *payload)
Test if I3C CCC payload is for broadcast.
Definition ccc.h:1371
int i3c_ccc_do_rstdaa_all(const struct device *controller)
Broadcast RSTDAA to reset dynamic addresses for all targets.
int i3c_ccc_do_setaasa_all(const struct device *controller)
Broadcast SETAASA to set all target's dynamic address to their static address.
int i3c_ccc_do_setmwl(const struct i3c_device_desc *target, const struct i3c_ccc_mwl *mwl)
Single target SETMWL to Set Maximum Write Length.
static int i3c_ccc_do_entas0(const struct i3c_device_desc *target)
Direct ENTAS0.
Definition ccc.h:1583
int i3c_ccc_do_getmrl(const struct i3c_device_desc *target, struct i3c_ccc_mrl *mrl)
Single target GETMRL to Get Maximum Read Length.
static int i3c_ccc_do_entas2_all(const struct device *controller)
Broadcast ENTAS2.
Definition ccc.h:1682
static int i3c_ccc_do_rstact_fmt2(const struct i3c_device_desc *target, enum i3c_ccc_rstact_defining_byte action)
Single target RSTACT to reset I3C Peripheral (Format 2).
Definition ccc.h:1461
i3c_ccc_getcaps_defbyte
Enum for I3C Get Capabilities (GETCAPS) Format 2 Defining Byte Values.
Definition ccc.h:872
static int i3c_ccc_do_entas2(const struct i3c_device_desc *target)
Direct ENTAS2.
Definition ccc.h:1613
static int i3c_ccc_do_getcaps_fmt1(const struct i3c_device_desc *target, union i3c_ccc_getcaps *caps)
Single target GETCAPS to Get Capabilities (Format 1).
Definition ccc.h:1899
static int i3c_ccc_do_entas3_all(const struct device *controller)
Broadcast ENTAS3.
Definition ccc.h:1696
int i3c_ccc_do_getmwl(const struct i3c_device_desc *target, struct i3c_ccc_mwl *mwl)
Single target GETMWL to Get Maximum Write Length.
static int i3c_ccc_do_rstact_fmt3(const struct i3c_device_desc *target, enum i3c_ccc_rstact_defining_byte action, uint8_t *data)
Single target RSTACT to reset I3C Peripheral (Format 3).
Definition ccc.h:1479
int i3c_ccc_do_setdasa(const struct i3c_device_desc *target, struct i3c_ccc_address da)
Set Dynamic Address from Static Address for a target.
int i3c_ccc_do_events_all_set(const struct device *controller, bool enable, struct i3c_ccc_events *events)
Broadcast ENEC/DISEC to enable/disable target events.
int i3c_ccc_do_events_set(struct i3c_device_desc *target, bool enable, struct i3c_ccc_events *events)
Direct CCC ENEC/DISEC to enable/disable target events.
#define I3C_CCC_BROADCAST_MAX_ID
Maximum CCC ID for broadcast.
Definition ccc.h:29
@ GETSTATUS_FORMAT_2_PRECR
PRECR - Alternate status format describing Controller-capable device.
Definition ccc.h:556
@ GETSTATUS_FORMAT_2_INVALID
Invalid defining byte.
Definition ccc.h:559
@ GETSTATUS_FORMAT_2_TGTSTAT
Target status.
Definition ccc.h:553
@ GETMXDS_FORMAT_2
GETMXDS Format 2.
Definition ccc.h:692
@ GETMXDS_FORMAT_1
GETMXDS Format 1.
Definition ccc.h:689
@ GETMXDS_FORMAT_3
GETMXDS Format 3.
Definition ccc.h:695
@ ENTTM_EXIT_TEST_MODE
Remove all I3C Devices from Test Mode.
Definition ccc.h:469
@ ENTTM_VENDOR_TEST_MODE
Indicates that I3C Devices shall return a random 32-bit value in the PID during the Dynamic Address A...
Definition ccc.h:474
@ GETMXDS_FORMAT_3_INVALID
Invalid defining byte.
Definition ccc.h:712
@ GETMXDS_FORMAT_3_CRHDLY
Delay parameters for a Controller-capable Device, and it's expected Activity State during a Controlle...
Definition ccc.h:709
@ GETMXDS_FORMAT_3_WRRDTURN
Standard Target Write/Read speed parameters, and optional Maximum Read Turnaround Time.
Definition ccc.h:704
@ I3C_CCC_RSTACT_RETURN_VIRTUAL_TARGET_INDICATION
Return Virtual Target Indication.
Definition ccc.h:1271
@ I3C_CCC_RSTACT_RETURN_TIME_TO_RESET_PERIPHERAL
Return Time to Reset Peripheral.
Definition ccc.h:1262
@ I3C_CCC_RSTACT_RETURN_TIME_TO_WHOLE_TARGET
Return Time to Reset Whole Target.
Definition ccc.h:1265
@ I3C_CCC_RSTACT_PERIPHERAL_ONLY
Reset the I3C Peripheral Only.
Definition ccc.h:1250
@ I3C_CCC_RSTACT_DEBUG_NETWORK_ADAPTER
Debug Network Adapter Reset.
Definition ccc.h:1256
@ I3C_CCC_RSTACT_NO_RESET
No Reset on Target Reset Pattern.
Definition ccc.h:1247
@ I3C_CCC_RSTACT_VIRTUAL_TARGET_DETECT
Virtual Target Detect.
Definition ccc.h:1259
@ I3C_CCC_RSTACT_RETURN_TIME_FOR_DEBUG_NETWORK_ADAPTER_RESET
Return Time for Debug Network Adapter Reset.
Definition ccc.h:1268
@ I3C_CCC_RSTACT_RESET_WHOLE_TARGET
Reset the Whole Target.
Definition ccc.h:1253
@ GETSTATUS_FORMAT_2
GETSTATUS Format 2.
Definition ccc.h:545
@ GETSTATUS_FORMAT_1
GETSTATUS Format 1.
Definition ccc.h:542
@ GETCAPS_FORMAT_1
GETCAPS Format 1.
Definition ccc.h:863
@ GETCAPS_FORMAT_2
GETCAPS Format 2.
Definition ccc.h:866
@ GETCAPS_FORMAT_2_CRCAPS
Controller handoff capabilities and features.
Definition ccc.h:880
@ GETCAPS_FORMAT_2_INVALID
Invalid defining byte.
Definition ccc.h:889
@ GETCAPS_FORMAT_2_TGTCAPS
Standard Target capabilities and features.
Definition ccc.h:874
@ GETCAPS_FORMAT_2_DBGCAPS
Debug-capable Device capabilities and features.
Definition ccc.h:886
@ GETCAPS_FORMAT_2_VTCAPS
Virtual Target capabilities and features.
Definition ccc.h:883
@ GETCAPS_FORMAT_2_TESTPAT
Fixed 32b test pattern.
Definition ccc.h:877
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
__UINT16_TYPE__ uint16_t
Definition stdint.h:89
Runtime device structure (in ROM) per driver instance.
Definition device.h:412
Payload for a single device address.
Definition ccc.h:490
uint8_t addr
Definition ccc.h:505
The active controller part of payload for DEFTGTS CCC.
Definition ccc.h:403
uint8_t addr
Dynamic Address of Active Controller.
Definition ccc.h:405
uint8_t dcr
Device Characteristic Register of Active Controller.
Definition ccc.h:408
uint8_t static_addr
Static Address of Active Controller.
Definition ccc.h:414
uint8_t bcr
Bus Characteristic Register of Active Controller.
Definition ccc.h:411
The target device part of payload for DEFTGTS CCC.
Definition ccc.h:423
uint8_t dcr
Device Characteristic Register of a I3C target device or a group.
Definition ccc.h:432
uint8_t addr
Dynamic Address of a target device, or a group address.
Definition ccc.h:425
uint8_t static_addr
Static Address of a target device or a group.
Definition ccc.h:442
uint8_t bcr
Bus Characteristic Register of a target device or a group.
Definition ccc.h:439
uint8_t lvr
Legacy Virtual Register for legacy I2C device.
Definition ccc.h:435
Payload for DEFTGTS CCC (Define List of Targets).
Definition ccc.h:453
struct i3c_ccc_deftgts_active_controller active_controller
Data describing the active controller.
Definition ccc.h:458
struct i3c_ccc_deftgts_target targets[]
Data describing the target(s) on the bus.
Definition ccc.h:461
uint8_t count
Number of Targets (and Groups) present on the I3C Bus.
Definition ccc.h:455
Payload for ENEC/DISEC CCC (Target Events Command).
Definition ccc.h:313
uint8_t events
Event byte:
Definition ccc.h:323
Payload for GETBCR CCC (Get Bus Characteristics Register).
Definition ccc.h:523
uint8_t bcr
Bus Characteristics Register.
Definition ccc.h:525
Payload for GETDCR CCC (Get Device Characteristics Register).
Definition ccc.h:531
uint8_t dcr
Device Characteristics Register.
Definition ccc.h:533
Payload for GETPID CCC (Get Provisioned ID).
Definition ccc.h:511
uint8_t pid[6]
48-bit Provisioned ID.
Definition ccc.h:517
Payload for SETMRL/GETMRL CCC (Set/Get Maximum Read Length).
Definition ccc.h:389
uint16_t len
Maximum Read Length.
Definition ccc.h:391
uint8_t ibi_len
Optional IBI Payload Size.
Definition ccc.h:394
Payload for SETMWL/GETMWL CCC (Set/Get Maximum Write Length).
Definition ccc.h:376
uint16_t len
Maximum Write Length.
Definition ccc.h:378
Payload structure for one CCC transaction.
Definition ccc.h:267
struct i3c_ccc_target_payload * payloads
Array of struct i3c_ccc_target_payload.
Definition ccc.h:303
struct i3c_ccc_payload::@229 ccc
size_t num_xfer
Total number of bytes transferred.
Definition ccc.h:291
uint8_t * data
Pointer to byte array of data for this CCC.
Definition ccc.h:280
struct i3c_ccc_payload::@230 targets
uint8_t id
The CCC ID (I3C_CCC_*).
Definition ccc.h:272
size_t num_targets
Number of targets.
Definition ccc.h:306
size_t data_len
Length in bytes for optional data array.
Definition ccc.h:283
One Bridged Target for SETBRGTGT payload.
Definition ccc.h:649
uint16_t id
16-bit ID for the bridged target.
Definition ccc.h:666
uint8_t addr
Dynamic address of the bridged target.
Definition ccc.h:656
Payload for SETBRGTGT CCC (Set Bridge Targets).
Definition ccc.h:676
uint8_t count
Number of bridged targets.
Definition ccc.h:678
struct i3c_ccc_setbrgtgt_tgt targets[]
Array of bridged targets.
Definition ccc.h:681
Payload structure for Direct CCC to one target.
Definition ccc.h:235
uint8_t addr
Target address.
Definition ccc.h:237
size_t data_len
Length in bytes for data.
Definition ccc.h:252
uint8_t rnw
0 for Write, 1 for Read
Definition ccc.h:240
uint8_t * data
Definition ccc.h:249
size_t num_xfer
Total number of bytes transferred.
Definition ccc.h:261
Structure describing a I3C target device.
Definition i3c.h:913
Misc utilities.
Macros to abstract toolchain specific capabilities.
Payload for GETCAPS CCC (Get Optional Feature Capabilities).
Definition ccc.h:899
union i3c_ccc_getcaps::@238 fmt1
uint8_t crcaps[2]
Defining Byte 0x91: CRCAPS Byte 1 CRCAPS1.
Definition ccc.h:965
uint8_t tgtcaps[4]
Defining Byte 0x00: TGTCAPS.
Definition ccc.h:944
uint8_t getcaps[4]
I3C v1.1+ Device Capabilities Byte 1 GETCAPS1.
Definition ccc.h:935
uint8_t gethdrcap
I3C v1.0 HDR Capabilities.
Definition ccc.h:908
uint8_t vtcaps[2]
Defining Byte 0x93: VTCAPS Byte 1 VTCAPS1.
Definition ccc.h:978
union i3c_ccc_getcaps::@239 fmt2
uint32_t testpat
Defining Byte 0x5A: TESTPAT.
Definition ccc.h:951
Payload for GETMXDS CCC (Get Max Data Speed).
Definition ccc.h:719
uint8_t maxrdturn[3]
Maximum Read Turnaround Time in microsecond.
Definition ccc.h:740
uint8_t maxrd
maxRd
Definition ccc.h:725
struct i3c_ccc_getmxds::@236 fmt2
uint8_t maxwr
maxWr
Definition ccc.h:722
struct i3c_ccc_getmxds::@237 fmt3
uint8_t wrrdturn[5]
Defining Byte 0x00: WRRDTURN.
Definition ccc.h:749
uint8_t crhdly1
Defining Byte 0x91: CRHDLY.
Definition ccc.h:756
struct i3c_ccc_getmxds::@235 fmt1
Payload for GETSTATUS CCC (Get Device Status).
Definition ccc.h:565
uint16_t precr
Defining Byte 0x91: PRECR.
Definition ccc.h:603
uint16_t tgtstat
Defining Byte 0x00: TGTSTAT.
Definition ccc.h:589
uint16_t status
Device Status.
Definition ccc.h:580
uint16_t raw_u16
Definition ccc.h:605
union i3c_ccc_getstatus::@234 fmt2
struct i3c_ccc_getstatus::@233 fmt1