cpu.h File Reference

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Macros
#define	SCTLR_MPU_ENABLE   (1 << 0)
#define	MODE_USR   0x10
#define	MODE_FIQ   0x11
#define	MODE_IRQ   0x12
#define	MODE_SVC   0x13
#define	MODE_ABT   0x17
#define	MODE_HYP   0x1a
#define	MODE_UND   0x1b
#define	MODE_SYS   0x1f
#define	MODE_MASK   0x1f
#define	E_BIT   (1 << 9)
#define	A_BIT   (1 << 8)
#define	I_BIT   (1 << 7)
#define	F_BIT   (1 << 6)
#define	T_BIT   (1 << 5)
#define	HIVECS   (1 << 13)
#define	CPACR_NA   (0U)
#define	CPACR_FA   (3U)
#define	CPACR_CP10(r)
#define	CPACR_CP11(r)
#define	FPEXC_EN   (1 << 30)
#define	DFSR_DOMAIN_SHIFT   (4)
#define	DFSR_DOMAIN_MASK   (0xf)
#define	DFSR_FAULT_4_MASK   (1 << 10)
#define	DFSR_WRITE_MASK   (1 << 11)
#define	DFSR_AXI_SLAVE_MASK   (1 << 12)
#define	VBAR_MASK   (0xFFFFFFE0U)
#define	SCTLR_M_BIT   BIT(0)
#define	SCTLR_A_BIT   BIT(1)
#define	SCTLR_C_BIT   BIT(2)
#define	SCTLR_I_BIT   BIT(12)
#define	IMP_CSCTLR_DFLW_SHIFT   (0)
#define	IMP_CSCTLR_IFLW_SHIFT   (8)
#define	IMP_CSCTLR(iway, dway)
#define	HSCTLR_RES1
#define	HACTLR_CPUACTLR   BIT(0)
#define	HACTLR_CDBGDCI   BIT(1)
#define	HACTLR_FLASHIFREGIONR   BIT(7)
#define	HACTLR_PERIPHPREGIONR   BIT(8)
#define	HACTLR_QOSR_BIT   BIT(9)
#define	HACTLR_BUSTIMEOUTR_BIT   BIT(10)
#define	HACTLR_INTMONR_BIT   BIT(12)
#define	HACTLR_ERR_BIT   BIT(13)
#define	HACTLR_INIT
#define	CNTV_CTL_ENABLE_BIT   BIT(0)
#define	CNTV_CTL_IMASK_BIT   BIT(1)
#define	ICC_SRE_ELx_SRE_BIT   BIT(0)
#define	ICC_SRE_ELx_DFB_BIT   BIT(1)
#define	ICC_SRE_ELx_DIB_BIT   BIT(2)
#define	ICC_SRE_ELx_EN_BIT   BIT(3)
	ICC SRE Enable.
#define	MPIDR_AFFLVL_MASK   (0xffU)
#define	MPIDR_AFF0_SHIFT   (0)
#define	MPIDR_AFF1_SHIFT   (8)
#define	MPIDR_AFF2_SHIFT   (16)
#define	MPIDR_AFF_MASK   GENMASK(23, 0)
	Mask for extracting Aff0, Aff1, and Aff2 fields from MPIDR.
#define	MPIDR_AFFLVL(mpidr, aff_level)
#define	GET_MPIDR()
#define	MPIDR_TO_CORE(mpidr)
#define	SGIR_TGT_MASK   (0xffff)
#define	SGIR_AFF1_SHIFT   (16)
#define	SGIR_AFF2_SHIFT   (32)
#define	SGIR_AFF3_SHIFT   (48)
#define	SGIR_AFF_MASK   (0xff)
#define	SGIR_INTID_SHIFT   (24)
#define	SGIR_INTID_MASK   (0xf)
#define	SGIR_IRM_SHIFT   (40)
#define	SGIR_IRM_MASK   (0x1)
#define	SGIR_IRM_TO_AFF   (0)
#define	GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt)

Macro Definition Documentation

A_BIT

#define A_BIT   (1 << 8)

CNTV_CTL_ENABLE_BIT

#define CNTV_CTL_ENABLE_BIT   BIT(0)

CNTV_CTL_IMASK_BIT

#define CNTV_CTL_IMASK_BIT   BIT(1)

CPACR_CP10

#define CPACR_CP10

(

r

)

Value:

(r << 20)

CPACR_CP11

#define CPACR_CP11

(

r

)

Value:

(r << 22)

CPACR_FA

#define CPACR_FA   (3U)

CPACR_NA

#define CPACR_NA   (0U)

DFSR_AXI_SLAVE_MASK

#define DFSR_AXI_SLAVE_MASK   (1 << 12)

DFSR_DOMAIN_MASK

#define DFSR_DOMAIN_MASK   (0xf)

DFSR_DOMAIN_SHIFT

#define DFSR_DOMAIN_SHIFT   (4)

DFSR_FAULT_4_MASK

#define DFSR_FAULT_4_MASK   (1 << 10)

DFSR_WRITE_MASK

#define DFSR_WRITE_MASK   (1 << 11)

E_BIT

#define E_BIT   (1 << 9)

F_BIT

#define F_BIT   (1 << 6)

FPEXC_EN

#define FPEXC_EN   (1 << 30)

GET_MPIDR

#define GET_MPIDR

(

)

Value:

read_sysreg(mpidr)

GICV3_SGIR_VALUE

#define GICV3_SGIR_VALUE	(		_aff3,
			_aff2,
			_aff1,
			_intid,
			_irm,
			_tgt )

Value:

((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) |    \
 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) |      \
 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) |    \
 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) |           \
 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) |               \
 ((_tgt) & SGIR_TGT_MASK))

HACTLR_BUSTIMEOUTR_BIT

#define HACTLR_BUSTIMEOUTR_BIT   BIT(10)

HACTLR_CDBGDCI

#define HACTLR_CDBGDCI   BIT(1)

HACTLR_CPUACTLR

#define HACTLR_CPUACTLR   BIT(0)

HACTLR_ERR_BIT

#define HACTLR_ERR_BIT   BIT(13)

HACTLR_FLASHIFREGIONR

#define HACTLR_FLASHIFREGIONR   BIT(7)

HACTLR_INIT

#define HACTLR_INIT

Value:

(HACTLR_ERR_BIT | HACTLR_INTMONR_BIT | \
HACTLR_BUSTIMEOUTR_BIT | HACTLR_QOSR_BIT | \
HACTLR_PERIPHPREGIONR | HACTLR_FLASHIFREGIONR | \
HACTLR_CDBGDCI | HACTLR_CPUACTLR)

HACTLR_INTMONR_BIT

#define HACTLR_INTMONR_BIT   BIT(12)

HACTLR_PERIPHPREGIONR

#define HACTLR_PERIPHPREGIONR   BIT(8)

HACTLR_QOSR_BIT

#define HACTLR_QOSR_BIT   BIT(9)

HIVECS

#define HIVECS   (1 << 13)

HSCTLR_RES1

#define HSCTLR_RES1

Value:

(BIT(29) | BIT(28) | BIT(23) | \
BIT(22) | BIT(18) | BIT(16) | \
BIT(11) | BIT(4)  | BIT(3))

I_BIT

#define I_BIT   (1 << 7)

ICC_SRE_ELx_DFB_BIT

#define ICC_SRE_ELx_DFB_BIT   BIT(1)

ICC_SRE_ELx_DIB_BIT

#define ICC_SRE_ELx_DIB_BIT   BIT(2)

ICC_SRE_ELx_EN_BIT

#define ICC_SRE_ELx_EN_BIT   BIT(3)

ICC SRE Enable.

ICC_SRE_ELx_SRE_BIT

#define ICC_SRE_ELx_SRE_BIT   BIT(0)

IMP_CSCTLR

#define IMP_CSCTLR	(		iway,
			dway )

Value:

((iway << IMP_CSCTLR_IFLW_SHIFT) | \
((dway << IMP_CSCTLR_DFLW_SHIFT)))

IMP_CSCTLR_DFLW_SHIFT

#define IMP_CSCTLR_DFLW_SHIFT   (0)

IMP_CSCTLR_IFLW_SHIFT

#define IMP_CSCTLR_IFLW_SHIFT   (8)

MODE_ABT

#define MODE_ABT   0x17

MODE_FIQ

#define MODE_FIQ   0x11

MODE_HYP

#define MODE_HYP   0x1a

MODE_IRQ

#define MODE_IRQ   0x12

MODE_MASK

#define MODE_MASK   0x1f

MODE_SVC

#define MODE_SVC   0x13

MODE_SYS

#define MODE_SYS   0x1f

MODE_UND

#define MODE_UND   0x1b

MODE_USR

#define MODE_USR   0x10

MPIDR_AFF0_SHIFT

#define MPIDR_AFF0_SHIFT   (0)

MPIDR_AFF1_SHIFT

#define MPIDR_AFF1_SHIFT   (8)

MPIDR_AFF2_SHIFT

#define MPIDR_AFF2_SHIFT   (16)

MPIDR_AFF_MASK

#define MPIDR_AFF_MASK   GENMASK(23, 0)

Mask for extracting Aff0, Aff1, and Aff2 fields from MPIDR.

MPIDR_AFFLVL

#define MPIDR_AFFLVL	(		mpidr,
			aff_level )

Value:

(((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)

MPIDR_AFFLVL_MASK

#define MPIDR_AFFLVL_MASK   (0xffU)

MPIDR_TO_CORE

#define MPIDR_TO_CORE

(

mpidr

)

Value:

((mpidr) & MPIDR_AFF_MASK)

SCTLR_A_BIT

#define SCTLR_A_BIT   BIT(1)

SCTLR_C_BIT

#define SCTLR_C_BIT   BIT(2)

SCTLR_I_BIT

#define SCTLR_I_BIT   BIT(12)

SCTLR_M_BIT

#define SCTLR_M_BIT   BIT(0)

SCTLR_MPU_ENABLE

#define SCTLR_MPU_ENABLE   (1 << 0)

SGIR_AFF1_SHIFT

#define SGIR_AFF1_SHIFT   (16)

SGIR_AFF2_SHIFT

#define SGIR_AFF2_SHIFT   (32)

SGIR_AFF3_SHIFT

#define SGIR_AFF3_SHIFT   (48)

SGIR_AFF_MASK

#define SGIR_AFF_MASK   (0xff)

SGIR_INTID_MASK

#define SGIR_INTID_MASK   (0xf)

SGIR_INTID_SHIFT

#define SGIR_INTID_SHIFT   (24)

SGIR_IRM_MASK

#define SGIR_IRM_MASK   (0x1)

SGIR_IRM_SHIFT

#define SGIR_IRM_SHIFT   (40)

SGIR_IRM_TO_AFF

#define SGIR_IRM_TO_AFF   (0)

SGIR_TGT_MASK

#define SGIR_TGT_MASK   (0xffff)

T_BIT

#define T_BIT   (1 << 5)

VBAR_MASK

#define VBAR_MASK   (0xFFFFFFE0U)