nxp,s32-spi

Vendor: NXP Semiconductors

Note

An implementation of a driver matching this compatible is available in drivers/spi/spi_nxp_s32.c.

Description

These nodes are “spi” bus nodes.

NXP S32 SPI controller

Properties

Properties not inherited from the base binding file.

Name

Type

Details

num-cs

int

 
The number of the Chip Select signals.

This property is required.

pinctrl-0

phandles

 
Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

This property is required.

pinctrl-names

string-array

 
Names for the provided states. The number of names needs to match the
number of states.

This property is required.

slave

boolean

 
Select if the SPI module is intended to be used in slave mode.

spi-sck-cs-delay

int

 
A delay in nanoseconds between the stop of clock signal and
deactivating Chip Select at the stop of transfer. If CS remains
asserted between transfer, this delay will be inserted between transfer.
If not set, the minimum supported delay is used.
This value will affect to all inner CS signals of SPI module when active.
This value will not be applied for CS lines controlled by GPIO.

spi-cs-sck-delay

int

 
A delay in nanoseconds between activating Chip Select and the start
of clock signal at the start of transfer. If CS remains asserted
between transfer, this delay will be inserted between transfer.
If not set, the minimum supported delay is used.
This value will affect to all inner CS signals of SPI module when active.
This value will not be applied for CS lines controlled by GPIO.

spi-cs-cs-delay

int

 
A delay in nanoseconds between deactivating Chip Select at the stop
of previous transfer and activating Chip Select at the start of
next transfer. If CS remains asserted between transfer, this delay
will not be inserted.
If not set, the minimum supported delay is used.
This value will affect to all inner CS signals of SPI module when active.
This value will not be applied for CS lines controlled by GPIO.

clock-frequency

int

 
Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

 
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

overrun-character

int

 
The overrun character (ORC) is used when all bytes from the TX buffer
are sent, but the transfer continues due to RX.

pinctrl-1

phandles

 
Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

 
Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

 
Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

 
Pin configuration/s for the fifth state. See pinctrl-0.