aesc,uart

Vendor: Aesc Silicon

Note

An implementation of a driver matching this compatible is available in drivers/serial/uart_aesc.c.

Description

These nodes are “uart” bus nodes.

Aesc Silicon UART (Universal Synchronous/Asynchronous Receiver/Transmitter)

The UART (Universal Asynchronous Receiver-Transmitter) IP Core is a configurable serial
communication interface designed to handle data transmission and reception. The core includes
an internal clock divider and supports flexible frame configurations, allowing for variable data
length, parity, and stop bit settings.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-frequency

int

Clock frequency information for UART operation

current-speed

int

Initial baud rate setting for UART

hw-flow-control

boolean

Set to enable RTS/CTS flow control at boot time

parity

string

Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd
and 2 for even parity, 3 for mark parity and 4 for space parity.
Default to none if not specified.

Default value: none

Legal values: 'none', 'odd', 'even', 'mark', 'space'

stop-bits

string

Sets the number of stop bits.

Legal values: '0_5', '1', '1_5', '2'

data-bits

int

Sets the number of data bits.

Legal values: 5, 6, 7, 8, 9