renesas,ra-mipi-dsi

Vendor: Renesas Electronics Corporation

Note

An implementation of a driver matching this compatible is available in drivers/mipi_dsi/dsi_renesas_ra.c.

Description

These nodes are “mipi-dsi” bus nodes.

Renesas RA MIPI DSI host

Properties

Top level properties

These property descriptions apply to “renesas,ra-mipi-dsi” nodes themselves. This page also describes child node properties in the following sections.

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
pll-div	int	PHY PLL divisor. Legal values: 1, 2, 3, 4
pll-mul-int	int	PHY PLL integer multiplier.
pll-mul-frac	string	PHY PLL fractional multiplier. Legal values: '0.00', '0.33', '0.66', '0.50'
lp-divisor	int	PHY PLL LP speed divisor.
ulps-wakeup-period	int	ULPS wakeup period.
video-mode-delay	int	Set the delay value inside DSI Host until the transfer begins.
timing	array	MIPI DSI timing parameter: <CLKSTPT CLKBFHT CLKKPT GOLPBKT>
phy-clock	int	MIPI PHY clock frequency. Should be set to ensure clock frequency is at least (pixel clock * bits per output pixel) / number of mipi data lanes

Child node properties

Name	Type	Details
t-init	int	Minimum duration of the TINIT state (Units: operation clock cycles). This property is required.
t-clk-prep	int	Duration of the clock lane LP-00 state (immediately before entry to the HS-0 state). This property is required.
t-hs-prep	int	Duration of the data lane LP-00 state (immediately before entry to the HS-0 state). This property is required.
t-lp-exit	int	Low-power transition time to High-Speed mode. This property is required.
dphytim4	array	Clock lane pre and post data timing parameter: <TCLKZERO TCLKPRE TCLKPOST TCLKTRL> This property is required.
dphytim5	array	High-Speed data lane timing parameter: <THSZERO THSTRL THSEXIT> This property is required.