atmel,sam-smc

Overview

Name:

atmel,sam-smc

Vendor:

Atmel Corporation

Used in:

List of boards using this compatible

Driver:

drivers/memc/memc_sam_smc.c

Description

Atmel Static Memory Controller (SMC).

The SMC allows to interface with static-memory mapped external devices such as
SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.

The SMC is clocked through the Master Clock (MCK) which is controlled by the
Power Management Controller (PMC).

The SMC controller can have up to 4 children defining the connected external
memory devices. The reg property is set to the device's Chip Select.
Device Tree example taken from the sam4_xplained board:

&smc {
  status = "okay";
  pinctrl-0 = <&smc_default>;
  pinctrl-names = "default";

  is66wv51216dbll@0 {
    reg = <0>;

    atmel,smc-data-bus-width = <8>;
    atmel,smc-write-mode = "nwe";
    atmel,smc-read-mode = "nrd";
    atmel,smc-setup-timing = <1 1 1 1>;
    atmel,smc-pulse-timing = <6 6 6 6>;
    atmel,smc-cycle-timing = <7 7>;
  };
};

The above example configures an is66wv51216dbll-55 device using the
controller's default 8-bit interface. The device is a low power static RAM
which uses NWE and NRD signals connected to the WE and OE inputs
respectively. Assuming that MCK is 120 MHz (CPU at full speed), each MCK
cycle is approximately 8.33 ns. Since the memory full cycle is 55 ns, as per
specification, it requires atmel,smc-cycle-timing of at least 7 cycles
(approximately 58.33 ns). The atmel,smc-cycle-timing is composed of three
parts: setup, pulse and hold. The setup is used to address the memory. The
pulse is the time used to read/write. The hold is used to release memory.
For the is66wv51216dbll-55 a minimum setup of 5 ns (1 cycle) with at least
45 ns (6 cycles) for CPU read/write and no hold time is required.
Note: Since no hold parameter is available at SMC the atmel,smc-cycle-timing
should have additional cycles to accommodate for hold values.

  No Hold Time:
  cycle-timing (7) = setup (1) + pulse (6) + hold (0)

  With 3 Hold Times:
  cycle-timing (10) = setup (1) + pulse (6) + hold (3)

A 16-bit CY62157EV30LL-45BVXI SRAM connected to a SAME70 SMC can be
configured as follows:

&smc {
  status = "okay";
  pinctrl-0 = <&smc_default>;
  pinctrl-names = "default";

  ext_sram_bus: ext-sram@0 {
    reg = <0>;

    atmel,smc-data-bus-width = <16>;
    atmel,smc-write-mode = "nwe";
    atmel,smc-read-mode = "nrd";
    atmel,smc-setup-timing = <1 1 1 1>;
    /*
     * MCK is 300 MHz on SAME70, so one cycle is approximately 3.33 ns.
     * 14 cycles is the minimum value that meets the 45 ns access time.
     */
    atmel,smc-pulse-timing = <14 14 14 14>;
    atmel,smc-cycle-timing = <15 15>;
    status = "okay";
  };
};

Finally, in order to make the memory available you will need to define new
memory device/s in DeviceTree:

sram1: sram@60000000 {
    compatible = "zephyr,memory-region", "mmio-sram";
    device_type = "memory";
    reg = <0x60000000 DT_SIZE_K(512)>;
    zephyr,memory-region = "SRAM1";
};

Properties

Top level properties

These property descriptions apply to “atmel,sam-smc” nodes themselves. This page also describes child node properties in the following sections.

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
pinctrl-0	phandles	Pin configuration/s for the first state. Content is specific to the selected pin controller driver implementation.
pinctrl-1	phandles	Pin configuration/s for the second state. See pinctrl-0.
pinctrl-2	phandles	Pin configuration/s for the third state. See pinctrl-0.
pinctrl-3	phandles	Pin configuration/s for the fourth state. See pinctrl-0.
pinctrl-4	phandles	Pin configuration/s for the fifth state. See pinctrl-0.
pinctrl-names	string-array	Names for the provided states. The number of names needs to match the number of states.

Child node properties

Name	Type	Details
reg	int	The device's SMC Chip Select number. Valid range: 0 - 3 This property is required. See Important properties for more information.
atmel,smc-write-mode	string	Select which signal is used for the write operation, either the chip select (ncs) or a dedicated write enable pin (nwe). The data is put on the bus during the pulse and hold steps of that signal. The internal data buffers are switched to output mode after the NCS_WR or NWE setup time. This property is required. Legal values: ncs, nwe
atmel,smc-read-mode	string	Select which signal is used for the read operation, either the chip select (ncs) or a dedicated output enable pin (nrd). The data is read from the bus during the pulse and hold steps of that signal. This property is required. Legal values: ncs, nrd
atmel,smc-setup-timing	array	This value is used to setup memory region (set address). The setup values is an array of the signals NWE, NCS_WR, NRD and NCS_RD where each value is configured in terms of MCK cycles. The SMC controller allows use of setups value of 0 (no delays) when consecutive reads/writes are used. Each value is encoded in 6 bits where the highest bit adds an offset of 128 cycles. The effective value for each element is: 128 x setup[5] + setup[4:0] This property is required.
atmel,smc-pulse-timing	array	This value is used to effectively read/write at memory region (pulse phase). The pulse value is an array of the signals NWE, NCS_WR, NRD and NCS_RD where each value is configured in terms of MCK cycles and a value of 0 is forbidden. Each value is encoded in 7 bits where the highest bit adds an offset of 256 cycles. The effective value for each element is: 256 x pulse[6] + pulse[5:0] This property is required.
atmel,smc-cycle-timing	array	SMC timing configurations in cycles for the total write and read length respectively. This value describes the entire write/read operation timing which is defined as: cycle = setup + pulse + hold Value has to be greater or equal to setup + pulse timing and is encoded in 9 bits where the two highest bits are multiplied with an offset of 256. Effective value for each element: 256 x cycle[8:7] + cycle[6:0] This property is required.
atmel,smc-data-bus-width	int	External data bus width used by the connected device. Legal values: 8, 16
atmel,smc-byte-access-type	string	Selects how byte-access cycles are handled by the connected device. Legal values: byte-select, byte-write
atmel,smc-page-mode	boolean	Enable page mode for the connected device when supported.
atmel,smc-page-size	int	Page size, in bytes, used when page mode is enabled. Legal values: 4, 8, 16, 32