adi,max32-hpb

Vendor: Analog Devices, Inc.

Note

An implementation of a driver matching this compatible is available in drivers/memc/memc_max32_hpb.c.

Description

MAX32 HyperBus (HPB) Memory Controller Interface

The HyperBus and Xccela Memory Controller interface is a high-speed, low-pin
count interface for connecting to one or more compatible external memory
devices. The external HyperBus or Xccela Bus memory device is mapped into the
memory space enabling direct code execution, data storage, or both.

The memory devices are defined as children of the HPB memory controller node.

&hpb {
    status = "okay";
    pinctrl-0 = <&hyp_cs0n_p1_11 &hyp_d0_p1_12 &hyp_d1_p1_15
                 &hyp_d2_p1_19 &hyp_d3_p1_20 &hyp_d4_p1_13
                 &hyp_d5_p1_16 &hyp_d6_p1_18 &hyp_d7_p1_21>;
    pinctrl-names = "default";

    mem@0 {
        reg = <0>;
        base-address = <0x60000000>;
        device-type = <ADI_MAX32_HPB_DEV_TYPE_HYPER_RAM>;
        config-regs =     <1>;
        config-reg-vals = <2>;
    };
};

Note: the values for most properties take values from
zephyr/dt-bindings/memory-controller/adi-max32-hpb.h header which will need to
be included.

Finally, in order to make the memory available you will need to define new
memory device/s in DeviceTree, e.g.:

sdram1: sdram@60000000 {
    compatible = "zephyr,memory-region", "mmio-sram";
    device_type = "memory";
    reg = <0x60000000 DT_SIZE_M(X)>;
    zephyr,memory-region = "SDRAM1";
};

Properties

Top level properties

These property descriptions apply to “adi,max32-hpb” nodes themselves. This page also describes child node properties in the following sections.

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
pinctrl-0	phandles	Pin configuration/s for the first state. Content is specific to the selected pin controller driver implementation. This property is required.
pinctrl-names	string-array	Names for the provided states. The number of names needs to match the number of states. This property is required.
enable-emcc	boolean	Enable the EMCC cache controller for the HyperBus memory devices.
pinctrl-1	phandles	Pin configuration/s for the second state. See pinctrl-0.
pinctrl-2	phandles	Pin configuration/s for the third state. See pinctrl-0.
pinctrl-3	phandles	Pin configuration/s for the fourth state. See pinctrl-0.
pinctrl-4	phandles	Pin configuration/s for the fifth state. See pinctrl-0.

Child node properties

Name	Type	Details
reg	int	This property is required. See Important properties for more information.
base-address	int	The address to which to map this memory device, e.g. 0x60000000. See the user guide for your specific SoC for the allowed range for mapping.
device-type	int	The type of attached memory device, i.e. Hyper Flash, Xccela PSRAM, or Hyper RAM. This property is required.
fixed-read-latency	boolean	Enable Xccela bus Fixed Read Latency. Should match the Latency Type configuration in the target PSRAM.
read-cs-high	int	The CS# high time, in clock cycles, between read operations.
write-cs-high	int	The CS# high time, in clock cycles, between write operations.
read-cs-setup	int	The CS# latency, in clock cycles, for read operations. This adds additional clock cycles after CS# goes low.
write-cs-setup	int	The CS# latency, in clock cycles, for write operations. This adds additional clock cycles after CS# goes low.
read-cs-hold	int	The CS# hold time, in clock cycles, between the completion of a read operation and the CS# deassertion.
write-cs-hold	int	The CS# hold time, in clock cycles, between the completion of a write operation and the CS# deassertion.
latency-cycles	int	For HyperRAM: set this property to match the external HyperRAM Read Latency Configuration Register value. For Xccela PSRAM: The value is adjusted based on `fixed-read-latency` property also being set.
config-regs	array	Configuration register addresses to set on the memory device during initialization.
config-reg-vals	array	Configuration register values to set on the memory device during initialization.