xlnx,axi-ethernet-1.00.a

Vendor: Xilinx

Note

An implementation of a driver matching this compatible is available in drivers/ethernet/eth_xilinx_axienet.c.

Description

Xilinx AXI 1G/2.5G Ethernet Subsystem base bindings.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-frequency

int

axistream-connected

phandle

Xilinx AXI DMA that is connected to the data streams.

This property is required.

axistream-control-connected

phandle

Xilinx AXI DMA that is connected to the control streams. Automatically generated by Xilinx' device tree generator. Included in the schema to prevent spurious warnings for such autogenerated device trees.

xlnx,rxcsum

int

RX checksum offloading. 0 = none, 2 = full. 1 = partial is not supported.

Legal values: 0, 2

xlnx,txcsum

int

TX checksum offloading. 0 = none, 2 = full. 1 = partial is not supported.

Legal values: 0, 2

local-mac-address

uint8-array

Specifies the MAC address that was assigned to the network device

zephyr,random-mac-address

boolean

Use a random MAC address generated when the driver is initialized.
Note that using this choice and rebooting a board may leave stale
MAC address in peers' ARP caches and lead to issues and delays in
communication.  (Use "ip neigh flush all" on Linux peers to clear
ARP cache.)

It is driver specific how the OUI octets are handled.

If set we ignore any setting of the local-mac-address property.

phy-handle

phandle

Specifies a reference to a node representing a PHY device.

phy-connection-type

string

Specifies the interface connection type between ethernet MAC and PHY.

Legal values: 'mii', 'rmii', 'gmii', 'rgmii', 'internal'