espressif,xtensa-lx6

Description

Espressif Xtensa LX6 CPU

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-source

int

Defines the CPU clock source, each corresponding to different frequencies:
- 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
- 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either
320 MHz or 480 MHz.
- 2: ESP32_CPU_CLK_SRC_RC_FAST - Employs an internal fast RC oscillator with
frequency of 17.5 MHz. 8 MHz for ESP32S2.
- 3: APLL_CLK - 16 Mhz ~ 128 MHz

This property is required.

Legal values: 0, 1, 2, 3

xtal-freq

int

Value of the external XTAL connected to ESP32.

This property is required.

Legal values: 40000000, 32000000, 26000000

device_type

string

Standard device_type identifying this node as a cpu. Required to maintain compatibility
with the IEEE 1275 standard as well as for DT_FOREACH_CPU family of devicetree macros to
identify cpu nodes within the "/cpus" parent node

Default value: cpu

zephyr,deferred-start

boolean

Do not start this CPU during kernel boot. By default, with CONFIG_SMP
the kernel starts every available CPU during start up. When this flag
is set the CPU is left un-started until architecture, SoC, board or
application code brings it up at run time with k_smp_cpu_start() (or
k_smp_cpu_resume()). The flag has no effect on the boot CPU.

clock-frequency

int

Clock frequency in Hz

cpu-power-states

phandles

List of power management states supported by this cpu

i-cache-line-size

int

i-cache line size

d-cache-line-size

int

d-cache line size

enable-method

string

Method by which a CPU in a disabled state is enabled. This property is
required for CPUs with a status property with a value of disabled. The
value may be one of the following:
- "psci": ARM Power State Coordination Interface.
- "spin-table": Standard DTSpec spin-table; requires cpu-release-addr.
- "[vendor],[method]": Vendor-defined method which describes the method a
  CPU is released from a disabled state.

For details, see "3.8.1 General Properties of /cpus/cpu* nodes" in
Devicetree Specification v0.4.

cpu-release-addr

array

Address of the release mailbox used by the spin-table enable-method.