ti,mspm0-pll

Vendor: Texas Instruments

Description

TI MSPM0 Phase Locked Loop

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.

p-div

int

pdiv is the pre-divider of the output. ref_in / pdiv * qdiv = VCO

This property is required.

Legal values: 1, 2, 4, 8

q-div

int

qdiv functions as a multiplier value for the ref_in / pdiv * qdiv = VCO
Valid Range: 2 - 128

This property is required.

clk0-div

int

CLK0 PLL output is only enabled if the divider is present. Use CLK0 on
the MSPM0 to output to the MCLK, UCLK, and CPUCLK
Valid Range: 1 - 16

clk1-div

int

CLK1 PLL output is only enabled if the divider is present. Use CLK1 on
the MSPM0 to output to the CANCLK, FCC, or output via EXCLK
Valid Range: 1 - 16

clk2x-div

int

CLK2X PLL output is only enabled if the divider is present. Use CLK2X on
the MSPM0 to output to the MCLK, UCLK, and CPUCLK instead of CLK0
Valid Range: 1 - 16