st,stm32mp13-pll-clock

Vendor: STMicroelectronics

Description

PLL node binding for STM32MP13 devices

It can be used to describe 4 different PLLs: PLL1, PLL2, PLL3 and PLL4.

These PLLs can take one of hse_ck, hsi_ck or csi_ck as input clock.
PLLM factor is used to set the input clock in this acceptable range.

Each PLL has one output clock whose frequency can be computed with the
following formula:

  f(PLL_P) = f(VCO clock) / (DIVP × DIVR × DIVQ)

    with f(VCO clock) = f(PLL clock input) × 2 × (((DIVN + 1) + (FRACV / 8192)) / DIVM1)

Note: To reduce the power consumption, it is recommended to configure the VCOx
      clock output to the lowest frequency.

The PLL1 output frequency must not exceed 2000 MHz.
The PLL2 output frequency must not exceed 1600 MHz.
The PLL3 output frequency must not exceed 800 MHz.
The PLL4 output frequency must not exceed 800 MHz.

Note: The CPU clock should not exceed 1Ghz so avoid configuring the PLL1 to more
than 1000 MHz or program the mpuss_ck mux to use the MPUDIV
(refer to the stm32mp13 reference manual for details)

div-m (aka DIVM1 + 1), div-p (aka DIVP + 1), div-q (aka DIVQ + 1),
div-r (aka DIVR + 1) have identical valid ranges for all 4 PLLs.
mul-n (aka DIVN + 1) valid range depends on the PLL
  PLL1: 31 - 125
  PLL2: 25 - 100
  PLL3: 25 - 200
  PLL4: 25 - 200

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

div-m

int

 
PLLx division factor (aka DIVM1 + 1) of the input clock divider
Valid range: 1 - 64

This property is required.

mul-n

int

 
PLLx multiplication factor (aka DIVN + 1) for VCO
Valid range: 25 - 200

This property is required.

div-p

int

 
PLLx_P division factor (aka DIVP + 1)
Valid range: 1 - 128

div-q

int

 
PLLx_Q division factor (aka DIVQ + 1)
Valid range: 1 - 128

div-r

int

 
PLLx_R division factor (aka DIVR + 1)
Valid range: 1 - 128

fracn

int

 
PLLx FRACV fractional latch
Valid range: 0 - 8191