st,stm32f4-rcc

Vendor: STMicroelectronics

Description

STM32F4 RCC (Reset and Clock controller).

Adds the STM32F4 Timer prescaler to the standard generic STM32 RCC.
For more description confere st,stm32-rcc.yaml

Properties

Properties not inherited from the base binding file.

Name

Type

Details

timpre

boolean

Timers clocks prescalers selection
Used to control the clock frequency of all the timers connected to APB1 and APB2 domain.
- When absent: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to
  a division factor of 1, TIMxCLK = HCKL. Otherwise, the timer clock frequencies are set to
  twice to the frequency of the APB domain to which the timers are connected:
  TIMxCLK = 2xPCLKx.
- When present: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured
  to a division factor of 1 or 2, TIMxCLK = HCKL. Otherwise, the timer clock frequencies are
  set to four times to the frequency of the APB domain to which the timers are connected:
  TIMxCLK = 4xPCLKx.

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.

Constant value: 2

clock-frequency

int

default frequency in Hz for clock output

This property is required.

ahb-prescaler

int

AHB prescaler. Defines actual core clock frequency (HCLK)
based on system frequency input.
The HCLK clocks CPU, AHB, memories and DMA.

This property is required.

Legal values: 1, 2, 4, 8, 16, 64, 128, 256, 512

apb1-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

apb2-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

undershoot-prevention

boolean

On some parts, it could be required to set up highest core frequencies
(>80MHz) in two steps in order to prevent undershoot.
This is done by applying an intermediate AHB prescaler before switching
System Clock source to PLL. Once done, prescaler is set back to expected
value.

Specifier cell names

  • clock cells: bus, bits