st,stm32f105-pll2-clock

Vendor: STMicroelectronics

Description

PLL2 node binding for Connectivity line devices (STM32F105/STM32F107)

Takes clk_hse as input clock, using prediv as prescaler.

Each PLL as its own output clock.

  f(PLL2CLK) = f(PLL2IN) / PREDIV * PLLMUL --> PLL (System Clock)

Properties

Properties not inherited from the base binding file.

Name

Type

Details

mul

int

 
PLL multiplication factor for output clock

This property is required.

Legal values: 8, 9, 10, 11, 12, 13, 14, 16, 20

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

prediv

int

 
Configurable prescaler
Valid range: 1 - 16

This property is required.

otgfspre

boolean

 
Optional PLL output divisor to generate a 48MHz USB clock.
When set, PLL output clock is not divided.
Otherwise, PLL output clock is divided by 1.5.